Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

Wong, H.-S. Philip; White, M.H.; Krutsick, T.J.; Booth, R.

doi:10.1016/0038-1101(87)90132-8

Cited by 294 publications

(109 citation statements)

References 41 publications

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“…The threshold voltage can be extracted from the peak of the second derivative of the total electron density per unit length (N t ) versus gate voltage [19] (similar to the transconductance change method [20]), while N t can be calculated by integrating the electron density over the channel cross-section and at the middle of the channel (x = L G /2; L G equals gate length) Fig. 2 shows the total electron density per unit length and the corresponding derivatives (normalized to the corresponding maximum values) for a GAA 15 nm wide Si NW MOSFET doped at 1 × 10 19 cm −3 , including quantum confinement.…”

Section: B Threshold Voltage Extraction Methodsmentioning

confidence: 99%

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

Najmzadeh

Sallèse

Berthomé

et al. 2012

IEEE Trans. Electron Devices

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Abstract-In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deplete more electrons than the flat sides or the channel center, when above (local accumulation) and below (local depletion) the flat-band voltage, respectively. On the contrary to the corner effect in the inversion mode (IM) devices, there is no major contribution of corners in the subthreshold current, and therefore, there is no subthreshold device behavior degradation (only one threshold voltage in the system). N-type channel doping levels of 1 × 10 19 , 5 × 10 18 , and 1 × 10 18 cm −3 were used for quasi-stationary device simulations of JL and AM MOSFETs, and corner effect was studied for 5, 10, and 15 nm wide equilateral triangular Si NW MOSFETs with a 2 nm SiO 2 gate oxide thickness (V DS = 0 V; T = 300 K). While the local quantum and classical electron density peaks are located in the corner regions above the flat-band voltage, reducing the channel doping and the channel cross-section was found to slightly suppress the normalized total accumulation electron density per unit length, N acc t /(CW eff ), in strong accumulation regime.

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Section: B Threshold Voltage Extraction Methodsmentioning

confidence: 99%

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

Najmzadeh

Sallèse

Berthomé

et al. 2012

IEEE Trans. Electron Devices

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“…The transconductance change (TC) [3] method is used to extract device threshold voltage at various temperatures. TC method, which utilizes the gate voltage at which the second derivative of the drain current versus gate voltage curve is a peak as the threshold voltage, has been proven to get a more accurate threshold voltage for various channel implant profiles, and is relatively insensitive to interface states, normal field mobility degradation and device series resistance [4].…”

Section: Methodsmentioning

confidence: 99%

CMOS 80 K-300 K SPICE Parameter for IRFPA Readout Circuit Design

Hwang

Lü

1996

J. Phys. IV France

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Abstract. This work presents the low temperature characteristics of commercial complementary-mentaloxide-semiconductor devices, which may be used in the readout electronics of the infrared focal plane array detector. Measurements are performed with the temperature calibration of the device under test. Two most important temperature dependent parameters of the drain current characteristics of the device, the threshold voltage and the carrier mobility are studied. Carrier fteeze out effect is considered in the threshold voltage calculation. Two kinds of empirical carrier mobility model are studied, and better model is included in the SPICE mobility model. A revised SPICE MOS level 3 parameter extraction scheme is proposed to extract new mobility model parameters.

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“…The threshold voltage of a MOSFET, in general, can be extracted using the transconductance change (TC) method [24], quasi-independent of series resistance and no need to any accurate analytical model. Interestingly, as shown in Fig.…”

Section: Threshold Voltage Extractionmentioning

confidence: 99%

“…13. V TH and low-field electron mobility extraction of an AMOSFET using the transconductance change [24] and ID= ffiffiffiffiffiffi g m p…”

Section: Threshold Voltage Extractionmentioning

confidence: 99%

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

Najmzadeh¹,

Bouvet²,

Grabinski³

et al. 2012

Solid-State Electronics

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a b s t r a c tIn this work we report dense arrays of accumulation-mode gate-all-around Si nanowire nMOSFETs with sub-5 nm cross-sections in a highly doped regime. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve P2.5 GPa uniaxial tensile stress in the Si nanowire is reported. The deeply scaled Si nanowire including such uniaxial tensile stress shows a low-field electron mobility of 332 cm 2 /V s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to %400 K and a V TH drift of À1.72 mV/K and an ionized impurity scattering-based mobility reduction were observed.

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Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFET's

Cited by 294 publications

References 41 publications

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

Local Volume Depletion/Accumulation in GAA Si Nanowire Junctionless nMOSFETs

CMOS 80 K-300 K SPICE Parameter for IRFPA Readout Circuit Design

Accumulation-mode gate-all-around si nanowire nMOSFETs with sub-5nm cross-section and high uniaxial tensile strain

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