Modeling digital substrate noise injection in mixed-signal IC's

Charbon, Edoardo; Miliozzi, P.; Carloni, Luca P.; Ferrari, A.; Sangiovanni‐Vincentelli, Alberto

doi:10.1109/43.748160

Cited by 63 publications

(21 citation statements)

References 14 publications

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“…each cell [10], [26]. The current injected by those cells located between two contacts is shifted to the previous contact to prevent overly optimistic results, as illustrated in Fig.…”

Section: Substrate Noise Analysis Methodologymentioning

confidence: 99%

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

Salman

Jakushokas

Friedman

et al. 2009

IEEE Trans. VLSI Syst.

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Abstract-A methodology is proposed to efficiently analyze substrate noise coupled to a sensitive block due to an aggressor digital block in large-scale mixed-signal circuits. The methodology is based on identifying voltage domains on the substrate by exploiting the small spatial voltage differences on the ground distribution network of the aggressor circuit. Specifically, similarly biased regions on the substrate short-circuited by the ground network are determined, and each of these regions is represented by a single equivalent input port to the substrate. The remaining ports within that domain are ignored to reduce the computational complexity of the extraction process. An algorithm with linear time complexity is proposed to merge those substrate contacts exhibiting a voltage difference smaller than a specified value, identifying a voltage domain. An equivalent contact is placed at the geometric mean of the merged contacts, ignoring all of the remaining ports such as the source/drain junctions of the devices. The ground network impedance is updated for each merged contact based on the proposed algorithm to maintain sufficient accuracy of the noise voltage. The substrate with reduced input ports is extracted using an existing extraction tool to analyze the noise at the sense node. As compared to the full extraction of an aggressor circuit, the methodology achieves a reduction of more than four orders of magnitude in the number of extracted substrate resistors with a peak-to-peak error of 24%.Index Terms-Ground noise, high level analysis methodology, mixed-signal ICs, substrate coupling noise, substrate extraction, substrate noise analysis.

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“…each cell [10], [26]. The current injected by those cells located between two contacts is shifted to the previous contact to prevent overly optimistic results, as illustrated in Fig.…”

Section: Substrate Noise Analysis Methodologymentioning

confidence: 99%

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

Salman

Jakushokas

Friedman

et al. 2009

IEEE Trans. VLSI Syst.

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“…The macromodel will be the basis of a noise evaluation methodology similar to Refs. [4,5,6]. The proportional macromodels for each gate are combined for complete circuit macromodel.…”

Section: Proposed Macromodelmentioning

confidence: 99%

“…• Mathematical models [2] • Equivalent switching models [3] • SubWave Methodology [4] • Universitat Polit'ecnica de Catalunya Methodology [5] • Susbstrate Waveform Analysis (SWAN) Methodology [6] • Input independent macromodels [7] • ADAMIN [8] Because of figure and page limitation, the details of the above-macromodels aren't presented here. One can find the details of mentioned-macromodels in the relative references.…”

Section: Background On Macromodelling Proposalsmentioning

confidence: 99%

Simulation of substrate coupling in mixed-signal IC's using an efficient and real-time macromodel

Karimi¹,

Mirzakuchaki²

2006

IEICE Electron. Express

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Substrate noise is a key problem in the design of large mixed-signal circuits. Estimating the interaction from large digital blocks and its effect on on-chip performance degradation is extremely important in mixed-signal IC design and is a major challenge in systemon-chip(SOC) design. In this paper, we address efficient methods and models to simulate substrate noise coupling at high level design with the real-time capability .Techniques to directly or indirectly compute the values of the elements in the cell macromodel are described. This approach makes it possible to predict substrate noise generation of large digital blocks in a very efficient and fast way and makes it compatible with the design flow of mixed-signal circuits. For verification, the macromodel accuracy is demonstrated in some example circuits.

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“…For large circuits, the simulation at transistor-level makes the exact switching noise evaluation very demanding in terms of memory and extraction time and even infeasible in several cases. To deal with this complexity, useful techniques have been proposed in the literature [20], [21]. The methodology of [21], for instance, uses a macromodel library of digital cells that includes package parasitics, in combination with VHDL switching events simulation, to generate the transient noise of digital circuits.…”

Section: A Spectral Estimation Of Switching Noisementioning

confidence: 99%

Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs

Koukab

Banerjee

Declercq

2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The substrate noise coupling problems in today's complex mixed-signal system-on-chip (MS-SOC) brings a new set of challenges for designers. In this paper, we propose a global methodology that includes an early verification in the design flow as well as a postlayout iterative optimization to deal with substrate noise, and helps designers to achieve a first silicon-success of their chips. An improved semi-analytical modeling technique exploiting the basic behaviors of this noise is developed. This method significantly accelerates the substrate modeling, avoids the dense matrix storage, and, hence, enables the implementation of an iterative noise-immunity optimization loop working at full-chip level. The integration of the methodology in a typical mixed-signal design flow is illustrated and its successful application to achieve a single-chip integration of a transceiver is demonstrated.

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Modeling digital substrate noise injection in mixed-signal IC's

Cited by 63 publications

References 14 publications

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits

Simulation of substrate coupling in mixed-signal IC's using an efficient and real-time macromodel

Modeling Techniques and Verification Methodologies for Substrate Coupling Effects in Mixed-Signal System-on-Chip Designs

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