Modeling and characterization of the low frequency noise behavior for amorphous InGaZnO thin film transistors in the subthreshold region

Cai, Minxi; Yao, Ruohe

doi:10.1063/1.4994152

Cited by 7 publications

(5 citation statements)

References 37 publications

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“…That is, NBS instabilities shift the transfer curve of the FET negatively, while PBS shifts it positively. To clearly explain the fundamental performance of IGZO transistors, a great deal of possible mechanisms have been proposed [ 14 , 15 , 16 , 17 , 18 , 19 ], for instance, charge trapping processes at the interfaces and/or in the dielectric, the creation and impact of deep traps in active layer, the absorption of oxygen or water molecules at the channel interface, the removal of oxygen interstitials, the capture of electrons by oxygen vacancies, the reduction of peroxide concentration, and the desorption and diffusion of hydrogen, and so on. However, due to the complexity of the dielectric layer and semiconductor layer, the origin of the bias instabilities in CAAC-IGZO FETs is still controversial.…”

Section: Introductionmentioning

confidence: 99%

Charge Trapping and Emission Properties in CAAC-IGZO Transistor: A First-Principles Calculations

Wang

et al. 2023

Materials

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The c-axis aligned crystalline indium-gallium-zinc-oxide field-effect transistor (CAAC-IGZO FET), exhibiting an extremely low off-state leakage current (~10−22 A/μm), has promised to be an ideal candidate for Dynamic Random Access Memory (DRAM) applications. However, the instabilities leaded by the drift of the threshold voltage in various stress seriously affect the device application. To better develop high performance CAAC-IGZO FET for DRAM applications, it’s essential to uncover the deep physical process of charge transport mechanism in CAAC-IGZO FET. In this work, by combining the first-principles calculations and nonradiative multiphonon theory, the charge trapping and emission properties in CAAC-IGZO FET have been systematically investigated. It is found that under positive bias stress, hydrogen interstitial in Al2O3 gate dielectric is probable effective electron trap center, which has the transition level (ε (+1/−1) = 0.52 eV) above Fermi level. But it has a high capture barrier about 1.4 eV and low capture rate. Under negative bias stress, oxygen vacancy in Al2O3 gate dielectric and CAAC-IGZO active layer are probable effective electron emission centers whose transition level ε (+2/0) distributed at −0.73~−0.98 eV and 0.69 eV below Fermi level. They have a relatively low emission barrier of about 0.5 eV and 0.25 eV and high emission rate. To overcome the instability in CAAC-IGZO FET, some approaches can be taken to control the hydrogen concentration in Al2O3 dielectric layer and the concentration of the oxygen vacancy. This work can help to understand the mechanisms of instability of CAAC-IGZO transistor caused by the charge capture/emission process.

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Section: Introductionmentioning

confidence: 99%

Charge Trapping and Emission Properties in CAAC-IGZO Transistor: A First-Principles Calculations

Wang

et al. 2023

Materials

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“…At low gate voltages, the carrier concentration in the channel near the interface is low, while many localized electrons are present in the conduction band-tailed states. 52 At this time, the capture and release of carriers by the band-tailed state has a significant effect on the mobility, while the effect of carrier capture and release by the defect trap at the interface is very limited due to the low carrier concentration. Therefore, the Δμ mode dominates the 1/f noise at low gate voltages.…”

Section: Resultsmentioning

confidence: 99%

Ultraviolet-Assisted Low-Thermal-Budget-Driven α-InGaZnO Thin Films for High-Performance Transistors and Logic Circuits

Zhang

Wang

et al. 2022

ACS Nano

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Developing a low-temperature fabrication strategy of an amorphous InGaZnO (α-IGZO) channel layer is a prerequisite for high-performance oxide-based thin film transistor (TFT) flexible device applications. Herein, an ultraviolet-assisted oxygen ambient rapid thermal annealing method (UV-ORTA), which combines ultraviolet irradiation with rapid annealing treatment in an oxygen atmosphere, was proposed to realize the achievement of high-performance α-IGZO TFTs at low temperature. Experimental results have confirmed that UV-ORTA treatment has the ability to suppress defects and obtain high-quality films similar to high-temperature-annealing-treated samples. α-IGZO/HfAlO TFTs with high-performance and low-voltage operating have been achieved at a low temperature of 180 °C for 200 s, including a high μsat of 23.12 cm2 V–1 S–1, large I on/off of 1.1 × 108, small subthreshold swing of 0.08 V/decade, and reliable stability under bias stress, respectively. As a demonstration of complex logic applications, a low-voltage resistor-loaded unipolar inverter based on an α-IGZO/HfAlO TFT has been built, demonstrating full swing characteristics and a high gain of 13.8. Low-frequency noise (LFN) characteristics of α-IGZO/HfAlO TFTs have been presented and concluded that the noise source tended to a carrier number fluctuation (ΔN) model from a carrier number and correlated mobility fluctuation (ΔN–Δμ) model. As a result, it can be inferred that the low-temperature UV-ORTA technique to improve α-IGZO thin film quality provides a facile and designable process for the integration of α-IGZO TFTs into a flexible electronic system.

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“…For device, local electrons in the conduction band tail state at low V GS can affect carrier capture and release on mobility more strongly than at the interface. [52] In this case, Δµ dominates the 1/f noise. Correspondingly, when providing the over V GS , the fermi level rises to the conduction band, leading to an increase in the channel carriers, which facilitates the capture of the interface trap carriers.…”

Section: Performance Regulation Of DC Nfns Based Tftsmentioning

confidence: 99%

Electrospun Stacked Dual‐Channel Transistors with High Electron Mobility Using a Planar Heterojunction Architecture

Jiang

et al. 2022

Adv Elect Materials

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Thin‐film transistors based on metal oxide semiconductors have become a mainstream technology for application in driving low‐cost backplanes of active matrix liquid crystal displays. Although significant progress has been made in traditional marketable devices based on physical vapor deposition derived metal oxides, it has still been hindered by low yield and poor compatibility. Fortunately, developing solution‐based 1D nanofiber networks to act as the fundamental building blocks for transistor has proven to be a simpler, higher‐throughput approach. However, oxide transistors based on such princesses suffer from degraded carrier mobility and operational instability, preventing the ability of such devices from replacing present polycrystalline Si technologies. Herein, it is shown that double channel heterojunction transistors with high electron mobility (>40 cm2 V−1 s−1) and operational stability can be achieved from electrospun double channels composed of In2O3 and ZnO layers. Adjusting the stacking order and the stacking density of In2O3 and ZnO layers can effectively optimize the interface electron trap, leading to the formation of 2D electron gas and the reduction of stress‐induced instability. These findings further elucidate the significant advance of electrospinning‐derived double channel heterojunction transistors toward practical applications for future low‐cost and high‐performance electronics.

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Modeling and characterization of the low frequency noise behavior for amorphous InGaZnO thin film transistors in the subthreshold region

Cited by 7 publications

References 37 publications

Charge Trapping and Emission Properties in CAAC-IGZO Transistor: A First-Principles Calculations

Charge Trapping and Emission Properties in CAAC-IGZO Transistor: A First-Principles Calculations

Ultraviolet-Assisted Low-Thermal-Budget-Driven α-InGaZnO Thin Films for High-Performance Transistors and Logic Circuits

Electrospun Stacked Dual‐Channel Transistors with High Electron Mobility Using a Planar Heterojunction Architecture

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