Model-based Design Space Exploration for RTES with SysML and MARTE

Abstract

The features of the emerging modeling languages for system design allow designers to build models of almost any kind of heterogeneous hardware-software systems, including Real Time Embedded Systems (RTES). An important goal to achieve is the implementation and use of these models in all the steps of a common design flow. One of these steps is the Design Space Exploration (DSE), which helps designers in discovering the optimal solutions among all possible combinations after mapping functional to architectural specifications; for RTES this step is particularly hard as it should include scheduling analysis in order to proof the time validity after the mapping. This paper presents some guidelines on how to use SysML and MARTE profiles to identify design points fulfilling the timing constraints of an RTES, and thus allowing to automate DSE analysis within the system design phase.

Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics

“…Furthermore, in [16] and [17] a MARTE-based methodology for abstract and formal specification of heterogeneous systems is introduced, supporting a safe use of concurrency and the automated generation of SystemC models. In [25], a methodology is described for supporting designers evaluating HW/SW partitioning solutions, specifically, to identify design points fulfilling the timing constraints. It proposes a way to have all possible combinations of system configurations in one set of diagrams.…”

A floorplan-aware interactive tool flow for NoC design and synthesis

“…However, they perform topology synthesis or floorplan selection as a push-button process, and do not allow incremental change or interactive selection of the most desirable design options. Some works [17] have proposed graphical interfaces for NoC design exploration. However, these works have focused on performing simulation analysis and exploring the design points at a high level of abstraction, which is a complementary to our work.…”

Combining SysML and Marte/CCSL to Model Complex Electronic Systems

“…This is endorsed by various distinguished researchers who have raised several concerns and opportunities regarding the combined use of SysML and MARTE profiles. Many researchers have proposed to use the SysML and UML profile for MARTE to model different sorts of electronic and embedded systems [22] - [24]. SysML and MARTE have been used together in several other projects like SATURN Project [26] and MeMVaTEx [27].…”