2016 International Conference on Information Systems Engineering (ICISE) 2016
DOI: 10.1109/icise.2016.13
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Combining SysML and Marte/CCSL to Model Complex Electronic Systems

Abstract: SystemVerilog is a popular hardware description and verification language aimed at designing and verifying present-day complex embedded systems. With the increasing number of design verification assertions, engineers always feel it difficult to manage the gap between the system specification and the design validation efforts and to cope with the time-to-market factors. An approach is presented for the modeling of system design as well as validation features using the UML standards like SysML, MARTE and CCSL. F… Show more

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Cited by 9 publications
(4 citation statements)
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“…The interdependencies among those S/S properties are conditional dependencies [17], i.e., violations of security properties can lead to the violations on safety properties. The events associated with those S/S properties can be interpreted as logical clocks in PrCcsl, which provides a way to express S/S properties in the logical time manner [16]. Therefore, S/S properties can be interpreted as logical timing constraints, i.e., the temporal and causality clock relations in PrCcsl.…”
Section: R3mentioning
confidence: 99%
See 1 more Smart Citation
“…The interdependencies among those S/S properties are conditional dependencies [17], i.e., violations of security properties can lead to the violations on safety properties. The events associated with those S/S properties can be interpreted as logical clocks in PrCcsl, which provides a way to express S/S properties in the logical time manner [16]. Therefore, S/S properties can be interpreted as logical timing constraints, i.e., the temporal and causality clock relations in PrCcsl.…”
Section: R3mentioning
confidence: 99%
“…Tadl2 specializes the time model of MARTE, the UML profile for Modeling and Analysis of Real-Time and Embedded systems [30]. MARTE provides Ccsl, a Clock Constraint Specification Language, that supports specification of both logical and dense timing constraints, as well as functional causality constraints [16,23]. A probabilistic extension of Ccsl, called PrCcsl [14], has been proposed to formally specify timing constraints associated with stochastic properties in weakly-hard real-time systems [4], i.e., a bounded number of constraints violations would not lead to system failures when the results of the violations are negligible.…”
Section: Introductionmentioning
confidence: 99%
“…These integrations are possible thanks to the use of metamodeling languages enabling the translation of domain‐specific SysML profiles to specific simulation environments (e.g., Modelica, DEVS, etc.). These tools have allowed, in particular, purely discrete systems such as embedded real‐time applications to be fully conceptualized at the abstract SysML level, to be translated to simulation code, to be formally verified, and eventually, in part, to be synthesized to machine code . A review of the state of the art in executable SysML models is proposed in Nikolaidou et al…”
Section: Sysml‐based Mbsd Of Cbpsmentioning
confidence: 99%
“…TADL2 specializes the time model of MARTE, the UML profile for Modeling and Analysis of Real-Time and Embedded systems [9]. MARTE provides CCSL [10], [11], which is the clock constraint specification language for specification of temporal constraints and functional causality properties [12]. In CCSL, time can be either chronometric (i.e., associated with physical time) or logical (i.e., related to events occurrences), which are represented by dense clocks and logical clocks, respectively.…”
Section: Introductionmentioning
confidence: 99%