Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters

Abstract

Abstract-The future of all kinds of applications that require a submilliwatt consumption strictly depends on the capability to meet design specifications at the minimum power costs. While several computer-aided-design tools are present to estimate the power consumption of modern ICs at transistor level, it is very difficult to predict the power at higher level. Given the reduced time-to-market of modern communication devices, it is very often needed to have accurate power estimations prior to the transistor-level design. Allocating a too conservative power budget to a block implies a possible poor tradeoff between the specifications of building blocks that constitute the system and their power consumption. For future power-constrained wireless devices (like wireless nodes in sensor networks), it is very important to have high-level models which can help the designer with the initial high-level choices without going into transistor-level design. One of the important blocks in modern communication devices, particularly for spread-spectrum systems, is the frequency synthesizer. In this paper, the first power-consumption model for an ultralow-power ROM-based direct digital frequency synthesizer has been developed, which can help the designer in the power optimization at a high level prior to transistor implementation.Index Terms-Direct digital synthesizer (DDS), frequency hopping (FH), low power, power estimation, sensor networks.

Pulse-width modulation based fully-digital transmitter with wide CF and high resolution

“…The existing quadrature IF PWM architecture [5] with high modulation resolution, is not apt for low CF cases due to IF interferences and faces intractable 3-level up-conversion implementation under single-supply process. The existing radiofrequency (RF) PWM [6] or direct digital frequency synthesizer (DDFS) [7] based transmitters aiming at low CF conditions, are not considered as fully-digital designs, since analogue feedback or mixed-signal configurations are used. The existing architecture employing out-phasing amplification technique [8] is not widely used in commerce due to limited phase-modulation resolution and strict matching requirements between the embedded dual paths.…”

Parallel PWMs Based Fully Digital Transmitter with Wide Carrier Frequency Range

“…The existing transmitters with quadrature [3, 4] or delay-line [5, 6] based intermediate-frequency (IF) pulse-width modulation (PWM), are not apt for low carrier-frequency (CF) applications, under which the band-pass filter (BPF) fails to suppress IF component or harmonics closer to the carrier. The existing radio-frequency (RF) PWM [7] or direct digital frequency synthesizer (DDFS) [8] based transmitters, aiming for low CF conditions, are not considered as fully digital designs, since analogue feedback or mixed-signal configurations are used. The existing architecture [9] employing outphasing amplification technique is not widely used in commerce due to strict matching requirements between dual paths and distortion and efficiency degradation caused by RF power combiner.…”