Parallel PWMs Based Fully Digital Transmitter with Wide Carrier Frequency Range

Zhou, Bo; Zhang, Kun; Zhou, Wei; Zhang, Yanjun; Liu, Dake

doi:10.1155/2013/373429

Cited by 2 publications

(8 citation statements)

References 11 publications

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“…By setting reasonable relations between the CF f C , IF f IF and BPF bandwidth B RF , following Eq. 2 [10], both IF aliasing or interference and CF harmonics are well suppressed by the external BPF with 6th-order transfer function, as shown in Fig. 1.…”

Section: Quadrature If Pwmmentioning

confidence: 82%

“…Detailed explanations of the IF-and CF-PWMs based on delay lines and multiplexers, can be referred in [3,10]. This work focuses on the proposed configurations to solve the core problems encountered in the existing designs, such as the envelope fidelity of CF PWM and the phase resolution of IF PWM.…”

Section: Architecturementioning

confidence: 99%

“…The existing architectures [3,4,8,10] for high CF applications feature poor phase-modulation resolution, since the baseband phase component modulates the rising-edge lag of the carrier clock, which is inversely limited by the carrier clock jitter. For instance, for the carrier clock of 1 GHz with the jitter of 20 ps, the delay-line depth or quantization point number should be less than 50, which sets low phase resolution of 7.2 o , or to ensure high phase resolution less than 3°, the CF will be lower than 420 MHz with given 20 ps carrier jitter.…”

Section: Highlightsmentioning

confidence: 99%

“…Different from the existing designs [6,9,10], the piecewise-linearization pre-correction arithmetic, apt for on-chip integration, is proposed to ensure the envelope fidelity for polar CF PWM.…”

Section: Highlightsmentioning

confidence: 99%

“…The existing CF PWM [9] avoids IF interferes but is unfit for high CF conditions considering limited pulse-width operation capability of the PA, and requires complex digital pre-correction arithmetic to ensure the envelopemodulation linearity. The existing parallel PWM implementation [10] with polar CF PWM and polar IF PWM, features wide CF range but encounters limited phasemodulation resolution where the carrier rising-edge lag on behalf of baseband phase component is limited by the carrier clock jitter, especially under high CF cases.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Pulse-width modulation based fully-digital transmitter with wide CF and high resolution

Zhang

Zhou

2015

Analog Integr Circ Sig Process

Self Cite

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The overview and design of fully-digital transmitters based on pulse-width modulation (PWM) are clarified. By employing the parallel architecture with quadrature intermediate-frequency (IF) PWM and precorrected polar carrier-frequency (CF) PWM, a fullydigital transmitter is proposed and designed in 180 nm CMOS, with wide CF and high modulation resolution. The presented PWMs are based on delay lines and multiplexers with the unit delay automatically calibrated. Inductive differential power combination with 2-level quadrature operation is proposed to accomplish the equivalent 3-level up-conversion for IF PWM. Piecewise-linearization correction technique is presented to ensure the envelopemodulation fidelity for CF PWM. For 8PSK based EDGE baseband signals, the proposed transmitter achieves a wide CF range of 2 M-1.5 GHz and a low error vector magnitude less than 3 %, with 20 dB spectrum optimized and higher modulation resolution in comparison to the existing designs. Excluding the power amplifiers, the presented implementation dissipates 120 lW from a 1.8 V power supply under the data rate of 270.833 kS/s or 812.5 kb/s, thus achieves the figure of merit of 0.44 nJ/S or 0.15 nJ/bit.

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Section: Quadrature If Pwmmentioning

confidence: 82%

Section: Architecturementioning

confidence: 99%

Section: Highlightsmentioning

confidence: 99%

Section: Highlightsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Pulse-width modulation based fully-digital transmitter with wide CF and high resolution

Zhang

Zhou

2015

Analog Integr Circ Sig Process

Self Cite

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Designing a Ring-VCO for RFID Transponders in 0.18 μm CMOS Process

Jalil

Reaz

Bhuiyan

et al. 2014

The Scientific World Journal

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In radio frequency identification (RFID) systems, performance degradation of phase locked loops (PLLs) mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for 2.42 GHz operated active RFID transponders compatible with IEEE 802.11 b/g, Bluetooth, and Zigbee protocols. For ease of integration and implementation of the module in tiny die area, a novel pseudodifferential delay cell based 3-stage ring oscillator has been introduced to fabricate the ring-VCO. In CMOS technology, 0.18 μm process is adopted for designing the circuit with 1.5 V power supply. The postlayout simulated results show that the proposed oscillator works in the tuning range of 0.5–2.54 GHz and dissipates 2.47 mW of power. It exhibits a phase noise of −126.62 dBc/Hz at 25 MHz offset from 2.42 GHz carrier frequency.

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Parallel PWMs Based Fully Digital Transmitter with Wide Carrier Frequency Range

Cited by 2 publications

References 11 publications

Pulse-width modulation based fully-digital transmitter with wide CF and high resolution

Pulse-width modulation based fully-digital transmitter with wide CF and high resolution

Designing a Ring-VCO for RFID Transponders in 0.18 μm CMOS Process

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