Designing a Ring-VCO for RFID Transponders in 0.18 <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M1"><mml:mrow><mml:mi mathvariant="bold-italic">μ</mml:mi></mml:mrow></mml:math>m CMOS Process

Jalil, Jubayer; Reaz, Mamun Bin Ibne; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah Farzana; Chang, Tae‐Gyu

doi:10.1155/2014/580385

Cited by 17 publications

(4 citation statements)

References 19 publications

(16 reference statements)

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“…A number of delay cells connected in a positive or regenerative feedback loop compose a main basis for ring oscillator structures [18]. In contrast with the single-ended counterpart, differential delay cells are widely used for providing both differential output signal and a higher level of common-mode rejection from supply disturbances and substrate induced-noise [19].…”

Section: Voltage-controlled Ring Oscillatormentioning

confidence: 99%

“…Thus, ring oscillator design process involves a proper selection of the adopted delay cell topology and the optimum number of delay cells. In general, a variable number of 2 to 4 stages are commonly applied for typical design in communication systems [18]. By applying a self-biased topology, the adopted structure for delay cell implementation is represented at schematic level through the diagram in Figure 3.…”

Section: Voltage-controlled Ring Oscillatormentioning

confidence: 99%

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Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

Pinto Jr,

Souza,

Castro

et al. 2023

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Section: Voltage-controlled Ring Oscillatormentioning

confidence: 99%

Section: Voltage-controlled Ring Oscillatormentioning

confidence: 99%

Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

Pinto Jr,

Souza,

Castro

et al. 2023

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“…In CMOS ring oscillators (single-ended or differential); a most common concern is the preferred method to generate better performance in terms of jitter, phasenoise, and total power dissipation. Single-ended CMOS ring oscillators phase noise and jitter are not strong functions of the number of stages [10][11][12]. However, the design is not done symmetrically or the design produces large noise, then a larger N will reduce the jitter.…”

Section: Figurementioning

confidence: 99%

Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

Rahman

Reaz²,

Marufuzzaman

et al. 2019

Informacije MIDEM

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Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm 2 . Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM. Načrtovanje tokovno omejenga oscilatorja nizkih moči in nizkega faznega šuma za RFID EEPROM nalepkeIzvleček: Poraba moči CMOS IC je izredno pomembna pri napravah nizkih moči, posebej še pri spominu RFID nalepk. V spošnem, spomin nalepk, kot je elektronsko izbrisljiv in programirljiv EEPROM, potrebuje generator interne ure za reguliranje internega napetostnega nivoja. Poleg številnih tipov osclatorjev je v članku opisan tokovno omejen obročni oscilator (CSRO), saj zaradi omejitve toka, ki zmanjšuje porabo moči. Načrtan CSRO uporablja tri stopnje za doseganje specificirane porabe moči. Simuliran oscilator potrebuje 4,9 mW pri napajalni napetosti 1,2 V in realizaciji v 130 nm Silterra CMOS tehnologiji. V primerjavi z drugimi oscilatorji ima najnižji fazni šum -119,38 dBc/Hz in majhno površino 0,001144 mm 2 . Predlagan oscilator je sposoben regulirati napetost EEPROM RFID nalepk.

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“…The comparators measure the smallest voltage differences in ADC's inputs, resolving the performance and the precision of any ADCs. An application that requires digital information recovery from analog signals, such as I/O receivers and radio frequency identification (RFID) memory circuits, widely uses high performance comparators to intensify a little input voltage to a big voltage level [ 3 , 4 ]. Moreover, digital logic circuits can detect these signals within a short period.…”

Section: Introductionmentioning

confidence: 99%

A High-Speed and Low-Offset Dynamic Latch Comparator

Rahman

Reaz

Yin

et al. 2014

The Scientific World Journal

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Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 μm × 59.70 μm.

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Designing a Ring-VCO for RFID Transponders in 0.18 μm CMOS Process

Cited by 17 publications

References 19 publications

Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

Dual-Delay-Path Ring Oscillator with Self-Biased Delay Cells for Clock Generation

Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

A High-Speed and Low-Offset Dynamic Latch Comparator

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