Personal communications require wireless nodes, which can transmit and receive reliably data under huge power constraints. Higher level of integration and reduction of power consumption can be achieved using a zero-IF architecture together with a wideband BFSK modulation scheme. Unfortunately FSK techniques performances degrade sharply in the presence of frequency offset. In this paper a comparison between potentially low power BFSK architectures is presented based on high level models. In depth analysis of four potentially low power demodulators shows that the architecture, which can assure rejection of large static offset with minimum increment in hardware complexity is the ST-DFT based demodulator. This will allow great reduction in power consumption avoiding acquisition and tracking of the offset at the receiver side.
In the last decade the amount of digital data generated in connection with digital devices such as cameras, media players and high-definition TVs has seen a significant growth. This requires tuners for home networking such as MoCA with increasingly large bandwidth. Though advanced CMOS technology allows for the design of high-speed circuits and systems that can meet the need for more bandwidth, 40nm feature sizes and beyond introduce new challenges in analog circuit design [1]. Moreover, dependence on environmental conditions of device spread and matching performance with parasitic coupling can drastically reduce the overall system performance.The integration of analog/RF circuits with the digital part in an SoC enables the use of inexpensive DSP power to calibrate non-idealities. Digitally-assisted RF allows for more power-and area-efficient systems that achieve good performance over process, temperature and supply (PVT) variations. This paper presents a calibration scheme that uses the available DSP power to perform the transmitter image, local oscillator feed-through (LOFT) and output power calibration by sub-sampling the transmitter spectrum. The system achieves an IR of 55dBc, a 40dBc LOFT and a ±0.6dB gain accuracy up to a 1.6GHz LO frequency.OFDM signals require an accurate control of LOFT, image level and delivered output power to meet the required performance. Though LOFT does not harm signal reception, a high LOFT level results in transmission of redundant energy and it reduces the receiver's dynamic range. A high image level due to I/Q imbalances affects the reception of the signal, degrading the receiver SNR. Finally, an accurate control of the transmitter output power removes the need for sophisticated power estimation procedures, reducing the system complexity.Transmitter LOFT or I/Q calibration can be performed at factory level [2] at the expense of a higher production cost or by dedicated mixed-signal circuitry [3,4] at the expense of extra chip area. The proposed calibration scheme reuses part of the receiver (the ADC) to perform all the calibration steps, minimizing chip area and production cost. Figure 24.1.1 shows the transmitter block diagram including the calibration path.The transmitter signal path consists of an I/Q baseband filter with a 1dB bandwidth tunable between 22MHz and 200MHz, a highly linear single-sideband mixer and a PA driver (PAD). The local oscillator (LO), used to up-convert the baseband signal, covers the frequencies between 50MHz and 1.6GHz.During calibration, either the upconversion mixer output (I/Q and LOFT calibration) or the PAD output (TX gain calibration) are looped-back to the RX ADC. A variable bandwidth buffer (VBB) is used to drive the RX ADC input and it is the only extra block required in the proposed calibration. The 12b ADC is clocked by an integer-N PLL driven by a 50MHz crystal-based reference signal. In the current prototype, CML buffers are used to drive the ADC outputs off-chip for data analysis. During calibration, a test tone (f BB ) is generated in ...
A novel frequency-hopping spread-spectrum transmitter architecture is presented that provides robust communications in the 915 MHz ISM band while dissipating very low power. The frequency-hopping front-end consists of a VCO, dividers and output stage. A base-band predistortion algorithm allows hopping with minimum hardware complexity. The TX front-end has been fabricated in Silicon-on-Anything (SOA) bipolar technology and a BFSK modulated wireless link using a dedicated receiver has been realized. A 1kbps, 1khop/s link with a BER smaller than 1.1 % has been achieved at -25 dBm output power while having 64 orthogonal channels. The synthesizer architecture (VCO+divider+base-band) dissipates only 870µA.
In the new era of personal communications, the increase the power consumption well above the allowed limit energy available for a wireless node is the limiting factor. for a self contained wireless node. Therefore, the design of a Furthermore wireless links should be robust even in the harsh minimum complexity hopping frequency synthesizer which indoor environment where fading, attenuation and interferences mnu ormplex homppin feun syntheszr, whoic can be severe. Spread-Spectrum techniques are largely used to hasqperformancescoprable w ith state-of-the-art hopping have a robust link, while Frequency-Hopping (FH) is the most frequency synthesizers, is required. This article is organized suitable for low data-rate applications. Unfortunately state-of-as follows. the-art FH systems are still far too complex and too power hungry Section II describes the state-of-the-art in FHSS systems. In to be implemented in a self contained wireless node. The proposed Section III a new approach towards a minimum complexity architecture simplifies considerably the hardware requirements ppoply for the hopping synthesizer achieving a current consumption of hopping isynesizer ispropse, while in S enI impleonly 900 ,uA (excluding the output buffer) from a 1.8 V power mentation issues and measurement results are given. Finally supply.concluding remarks are given in Section V.
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