Power-effective ROM-less DDFS Design Approach with High SFDR Performance

Wang, Chua‐Chin; Sulistiyanto, Nanang; Shih, Hsiang Yu; Lin, Yu Cheng; Wang, Wei

doi:10.1007/s11265-019-01460-x

Cited by 3 publications

(1 citation statement)

References 11 publications

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“…SPWM inverters are widely used in industrial fields, and many three-phase loads require fast and efficient variable voltage and variable frequency power supplies [1][2][3] . Traditional SPWM inverter control is generally completed by digital circuits and analog circuits [4][5][6] . However, this control method not only requires a large number of components and various types of components, but also has a complicated design process, a long development cycle, and a relatively high cost.…”

Section: Introductionmentioning

confidence: 99%

Design of three-phase SPWM inverter controller based on FPGA

Sun

Lu²,

Li³

2022

6th International Conference on Mechatronics and Intelligent Robotics (ICMIR2022)

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By improving the realization method of inverter, a realization scheme of SPWM (Sinusoidal Pulse Width Modulation) controller based on Field Programmable Gate Array (FPGA) is proposed. The design of the controller is mainly composed of a waveform generator and a SPWM generator. It has the function of frequency modulation and amplitude modulation. The dead time can be set according to the hardware environment, and it has the characteristics of closed-loop adjustment. The modular design method makes the whole control system simpler and more reliable. The function and timing simulation of the designed controller is carried out, and the simulation results verify the correctness and feasibility of the design.

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Section: Introductionmentioning

confidence: 99%

Design of three-phase SPWM inverter controller based on FPGA

Sun

Lu²,

Li³

2022

6th International Conference on Mechatronics and Intelligent Robotics (ICMIR2022)

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Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology

Ellaithy

2022

J CIRCUIT SYST COMP

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Direct digital frequency synthesizer (DDFS) have been proposed extensively as the main structure block in modern wireless communication systems for the complex demodulation process. One of the major design constraints of the performance of DDFS is power dissipation. In this work, efficient implementation of the phase to Sine/Cosine mapping of DDFS is proposed to accomplish less amount hardware and low power dissipation based on the logarithm scheme. The logarithm arithmetic is exploited in the implementations of the sinusoidal functions to simplify the generation process to attain a low-power and low-cost DDFS. The generated Sine/Cosine function is approximated based on the Taylor polynomial approximations. The proposed architecture utilizes efficient logarithm converter units to implement the phase to Sine/Cosine mapping instead of using costly multipliers and squarers. The proposed logarithm-based DDFS scheme demonstrates a reduction in power dissipation with respect to previously proposed work. The proposed architecture produces a spurious-free dynamic range (SFDR) of up to 117 dBc.

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Optimized Design of Direct Digital Frequency Synthesizer Based on Hermite Interpolation

Zhou,

Xu,

Zhang

2024

Sensors

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To address the issue of suboptimal spectral purity in Direct Digital Frequency Synthesis (DDFS) within resource-constrained environments, this paper proposes an optimized DDFS technique based on cubic Hermite interpolation. Initially, a DDFS hardware architecture is implemented on a Field-Programmable Gate Array (FPGA); subsequently, essential interpolation parameters are extracted by combining the derivative relations of sine and cosine functions with a dual-port Read-Only Memory (ROM) structure using the cubic Hermite interpolation method to reconstruct high-fidelity target waveforms. This approach effectively mitigates spurious issues caused by amplitude quantization during the DDFS digitalization process while reducing data node storage units. Moreover, this paper introduces single-quadrant ROM compression technology to further diminish the required storage space. Experimental results indicate that, compared to traditional DDFS methods, the optimization scheme proposed in this work achieves a ROM resource compression ratio of 1792:1 and a 14-bit output Spurious-Free Dynamic Range (SFDR) of −88.134 dBc, effectively enhancing amplitude quantization precision and significantly lowering spurious levels. This significantly improves amplitude quantization precision and reduces spurious levels. The proposed scheme demonstrates notable advantages in both spectral performance and resource utilization efficiency, making it highly suitable for resource-constrained embedded systems and high-performance applications such as radar and communication systems.

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Power-effective ROM-less DDFS Design Approach with High SFDR Performance

Cited by 3 publications

References 11 publications

Design of three-phase SPWM inverter controller based on FPGA

Design of three-phase SPWM inverter controller based on FPGA

Low-Power Low-Cost Direct Digital Frequency Synthesizer Using 90 nm CMOS Technology

Optimized Design of Direct Digital Frequency Synthesizer Based on Hermite Interpolation

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