Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC

Zhou, Shi-Ting; Katariya, Sumeet; Ghasemi, Hamid; Draper, Stark C.; Kim, Nam Sung

doi:10.1109/iccd.2010.5647605

Cited by 27 publications

(47 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For instance, Zhou et al describe six different sizes of 6T SRAM cells in 32 nm technology, and how their probabilities of failure change with the voltage supply and the size of the constituent transistors [42]. We will take this study as a reference for the rest of the paper.…”

Section: Process Variation In Sram Cellsmentioning

confidence: 99%

“…Larger transistors reduce V th variability, since nonuniformities in channel doping average out, and result in more robust devices with a lower probability of failure [42]. Another approach to reducing variability is to add assist read/write circuitry by increasing the number of transistors per SRAM cell.…”

Section: Related Workmentioning

confidence: 99%

“…Khan et al propose a mixed-cell memory design, where some of the cells are more robust and failure-resistant and, therefore, more reliable candidates to store dirty cache blocks, while the rest are designed using traditional cells [21]. Zhou et al combine spare cells, heterogeneous cell sizes, and ECCs into a hybrid design to improve on the effectiveness obtained by any of the techniques applied alone [42].…”

Section: Related Workmentioning

confidence: 99%

“…Circuit-level techniques improve the reliability of the SRAM cell in low-voltage operation by increasing its size or by adding assist circuitry [24], [42]. These come at the cost of an increase in power consumption and array area, which is not practical for large structures such as the on-chip LLC.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Ferrerón

Gracia

Alastruey-Benedé

et al. 2016

IEEE Trans. Comput.

View full text Add to dashboard Cite

Abstract-Scaling supply voltage to values near the threshold voltage allows a dramatic decrease in the power consumption of processors; however, the lower the voltage, the higher the sensitivity to process variation, and, hence, the lower the reliability. Large SRAM structures, like the last-level cache (LLC), are extremely vulnerable to process variation because they are aggressively sized to satisfy high density requirements. In this paper, we propose Concertina, an LLC designed to enable reliable operation at low voltages with conventional SRAM cells. Based on the observation that for many applications the LLC contains large amounts of null data, Concertina compresses cache blocks in order that they can be allocated to cache entries with faulty cells, enabling use of 100% of the LLC capacity. To distribute blocks among cache entries, Concertina implements a compression-and fault-aware insertion/replacement policy that reduces the LLC miss rate. Concertina reaches the performance of an ideal system implementing an LLC that does not suffer from parameter variation with a modest storage overhead. Specifically, performance degrades by less than 2%, even when using small SRAM cells, which implies over 90% of cache entries having defective cells, and this represents a notable improvement on previously proposed techniques.

show abstract

Section: Process Variation In Sram Cellsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Ferrerón

Gracia

Alastruey-Benedé

et al. 2016

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…Other authors propose splitting the cache into different modules [11]. Zhou et al [23] propose downsizing 6T cells of large on-chip caches combined with EDC techniques and extra cells to guarantee a target yield. In general, those techniques are unsuitable for our market since they fail to operate reliably at ULE mode.…”

Section: Related Workmentioning

confidence: 99%

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Marić¹,

Abella²,

Valero³

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

View full text Add to dashboard Cite

Abstract-Semiconductor technology evolution enables the design of sensor-based battery-powered ultra-low-cost chips (e.g., below 1 C) required for new market segments such as body, urban life and environment monitoring. Caches have been shown to be the highest energy and area consumer in those chips.This paper proposes a novel, hybrid-operation (high Vcc, ultralow Vcc), single-Vcc domain cache architecture based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with Error Detection and Correction (EDC) features for high reliability and performance predictability. Our architecture is proven to largely outperform existing solutions in terms of energy and area.

show abstract

Static probabilistic worst case execution time estimation for architectures with faulty instruction caches

Hardy

Puaut²

2014

Real-Time Syst

View full text Add to dashboard Cite

Semiconductor technology evolution suggests that permanent failure rates will increase dramatically with scaling, in particular for SRAM cells. While well known approaches such as error correcting codes exist to recover from failures and provide fault-free chips, they will not be affordable anymore in the future due to their non-scalable cost. Consequently, other approaches like fine grain disabling and reconfiguration of hardware elements (e.g. individual functional units or cache blocks) will become economically necessary. This fine-grain disabling will lead to degraded performance compared to a fault-free execution. To the best of our knowledge, all static worst-case execution time (WCET) estimation methods assume fault-free architectures. Their result is not safe anymore when using fine grain disabling of hardware components, which degrades performance. In this paper we provide the first method that statically calculates a probabilistic WCET bound in the presence of permanent faults in instruction caches. The proposed method, from a given program, cache configuration and probability of cell failure, derives a probabilistic WCET bound. The proposed method, because it relies on static analysis, is guaranteed to identify the longest program path, its probabilistic nature only stemming from the presence of faults. The method is computationally tractable because it does not require an exhaustive enumeration of the possible locations of faulty cache blocks. Experimental results show that it provides WCET estimates very close to, but never below, the method that derives probabilistic WCETs by enumerating all possible locations of faulty cache blocks. The proposed method not only allows to quantify the impact of permanent faults on WCET estimates, but also can be used in architectural exploration frameworks to select the most appropriate fault management mechanisms.

show abstract

Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC

Cited by 27 publications

References 17 publications

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Static probabilistic worst case execution time estimation for architectures with faulty instruction caches

Contact Info

Product

Resources

About