Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Marić, Bojan; Abella, Jaume; Valero, Mateo

doi:10.7873/date.2013.193

Cited by 7 publications

(13 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Note again that in this brief, we consider only ULE mode operation. For more details about HP mode, we refer the reader to [12].…”

Section: A Methodologymentioning

confidence: 99%

“…Our proposed hybrid cache architecture [12] overcomes the inefficiency of the large SRAM cells (e.g., 10T) used in the baseline cache in a manner that delivers energy and area efficiency without jeopardizing reliability levels to still provide strong performance guarantees. We replace energy-hungry SRAM cells (e.g., 10T [8]) in ULE ways by more energy-efficient and smaller SRAM cells (e.g., 8T [13]) enhanced with EDC codes to keep the same reliability levels, as needed at ULE mode.…”

Section: B Proposed Hybrid Cache Architecturementioning

confidence: 99%

“…In [12], we proposed a single-V cc domain L1 cache architecture for reliable hybrid-voltage operation, which meets all stringent needs of our target market. Our cache architecture has shown that replacing energy-hungry SRAM cells (e.g., 10T [8]) by more energy-efficient and smaller SRAM cells (e.g., 8T [13]) enhanced with error detection and correction (EDC) features provides significant energy and area savings without jeopardizing reliability levels to still provide strong performance guarantees.…”

Section: Introductionmentioning

confidence: 99%

“…Multiple V cc domains may be used to implement HP and ULE modes, but they increase design cost and complexity to unaffordable levels for our target market. Alternatively, cheap solutions based on a single-V cc domain have been demonstrated recently [10]- [12]. Cache memories are used to increase the efficiency of the system by reducing the number of slow and energy-hungry memory accesses.…”

Section: Introductionmentioning

confidence: 99%

“…OVERVIEW OF THE PROPOSED HYBRID CACHE ARCHITECTURE In this section, we first describe the chosen baseline cache architecture. Then, we present the proposed hybrid cache architecture [12].…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes

Maric

Abella

Valero

2014

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

The increasing demand for highly miniaturized batterypowered ultralow cost systems (e.g., below 1 dollar) in emerging applications such as body, urban life and environment monitoring, and so on, has introduced many challenges in chip design. Such applications require high performance occasionally and very little energy consumption during most of the time to extend battery lifetime. In addition, they require real-time guarantees. Caches have been shown to be the most critical blocks in these systems due to their high energy/area consumption and hard-to-predict behavior. New, simple, hybrid-voltage operation (high V cc and ultralow V cc ), single-V cc domain L1 cache architectures based on replacing energy-hungry bitcells (e.g., 10T) by more energy-efficient and smaller cells (e.g., 8T) enhanced with error detection and correction codes have been recently proposed. Such designs provide significant energy and area efficiency without jeopardizing reliability levels to still provide strong performance guarantees. In this brief, we analyze the efficiency of these designs during ultralow voltage operation. We identify the limits of such approaches by finding an energy-optimal voltage region through experimental models. The experimental results show that area efficiency is always achieved in the range 200-400 mV, whereas both energy and area gains occur above 250 mV, i.e., in near-threshold regime.

show abstract

“…Note again that in this brief, we consider only ULE mode operation. For more details about HP mode, we refer the reader to [12].…”

Section: A Methodologymentioning

confidence: 99%

Section: B Proposed Hybrid Cache Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…OVERVIEW OF THE PROPOSED HYBRID CACHE ARCHITECTURE In this section, we first describe the chosen baseline cache architecture. Then, we present the proposed hybrid cache architecture [12].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes

Maric

Abella

Valero

2014

IEEE Trans. VLSI Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

iPatch: Intelligent fault patching to improve energy efficiency

Palframan

Kim

Lipasti

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

View full text Add to dashboard Cite

Dynamic voltage and frequency scaling can provide substantial energy savings but is limited by SRAM since some cells will fail at very low voltages. Due to process variation effects, a small subset of SRAM cells will be more sensitive to voltage reduction, requiring increased margins and limiting energy savings. Since large arrays like caches are most vulnerable to cell failures, recent proposals suggest disabling failing portions of the cache to enable low voltage operation. Although such approaches save power, energy reduction is limited because reducing the effective cache size increases program runtimes. In this paper, we present iPatch, a solution to regain this lost performance and enable energy savings by exploiting the redundancy inherent in superscalar processors. By relying on existing microarchitectural structures and mechanisms to "patch" the faulty parts of caches, we enable further energy reduction with minimal overhead and complexity. Furthermore, because no critical paths or circuits are affected by our implementation, there is no impact on normalvoltage operation. For high cell failure rates, our results show significant energy savings with iPatch as well as an 18% reduction in energy-delay product compared to prior work. 428978-1-4799-8930-0/15/$31.00 ©2015 IEEE

show abstract

A Survey of Architectural Techniques for Near-Threshold Computing

Mittal

2015

J. Emerg. Technol. Comput. Syst.

View full text Add to dashboard Cite

Energy efficiency has now become the primary obstacle in scaling the performance of all classes of computing systems. Low-voltage computing, specifically, near-threshold voltage computing (NTC), which involves operating the transistor very close to and yet above its threshold voltage, holds the promise of providing many-fold improvement in energy efficiency. However, use of NTC also presents several challenges such as increased parametric variation, failure rate, and performance loss. This article surveys several recent techniques that aim to offset these challenges for fully leveraging the potential of NTC. By classifying these techniques along several dimensions, we also highlight their similarities and differences. It is hoped that this article will provide insights into state-of-the-art NTC techniques to researchers and system designers and inspire further research in this field.

show abstract

Efficient Cache Architectures for Reliable Hybrid Voltage Operation Using EDC Codes

Cited by 7 publications

References 18 publications

Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes

Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes

iPatch: Intelligent fault patching to improve energy efficiency

A Survey of Architectural Techniques for Near-Threshold Computing

Contact Info

Product

Resources

About