Proceedings of the Fifth Asian Test Symposium (ATS'96)
DOI: 10.1109/ats.1996.555153
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Minimal delay test sets for unate gate networks

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Cited by 7 publications
(7 citation statements)
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“…[Theorem 1] (Universal test set) [9] For any monotone combinational circuits, testing using V 0 [ V 1 as a test set is capable of detecting any path delay faults which aect normal operation of the circuits.…”
Section: : Related Workmentioning
confidence: 99%
“…[Theorem 1] (Universal test set) [9] For any monotone combinational circuits, testing using V 0 [ V 1 as a test set is capable of detecting any path delay faults which aect normal operation of the circuits.…”
Section: : Related Workmentioning
confidence: 99%
“…Since inverter-free two-rail logic circuits are unate, the universal test set is available for delay fault testing on two-rail logic circuits. However, the studies [9,10] target not two-rail logic circuits but unate circuits. There are still many important and useful but not claried properties relating to delay fault testing on two-rail logic circuits.…”
Section: : Introductionmentioning
confidence: 98%
“…From these, delay fault testing on two-rail logic circuits is important. In [9,10], a universal delay fault test set for unate circuits were shown. Since inverter-free two-rail logic circuits are unate, the universal test set is available for delay fault testing on two-rail logic circuits.…”
Section: : Introductionmentioning
confidence: 99%
“…No previous scan design has focused on TRLCs. Sparmann et al researched the testability of unate gate network [7], [8]. Since TRLCs are unate, their results are applicable to TRLCs.…”
Section: Introductionmentioning
confidence: 99%