Minimal delay test sets for unate gate networks

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing

2008

Two-rail logic circuits can be eciently tested b y non-codeword v e ctor pairs. However, non-codeword vector pairs may sensitize some path delay faults which aect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with non-codeword v e ctor pairs may be over-testing. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the over-testing.

Section: : Related Workmentioning

confidence: 99%

Path Delay Fault Test Set for Two-Rail Logic Circuits

2008 14th IEEE Pacific Rim International Symposium on Dependable Computing

2008

“…Since inverter-free two-rail logic circuits are unate, the universal test set is available for delay fault testing on two-rail logic circuits. However, the studies [9,10] target not two-rail logic circuits but unate circuits. There are still many important and useful but not claried properties relating to delay fault testing on two-rail logic circuits.…”

Section: : Introductionmentioning

confidence: 98%

“…From these, delay fault testing on two-rail logic circuits is important. In [9,10], a universal delay fault test set for unate circuits were shown. Since inverter-free two-rail logic circuits are unate, the universal test set is available for delay fault testing on two-rail logic circuits.…”

Section: : Introductionmentioning

confidence: 99%

Delay Fault Testability on Two-Rail Logic Circuits

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

2008

The importance o f r edundant technologies for improving dependability and delay fault testability are g r owing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and discusses testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is just twice t h a t i n o r dinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are m o r e testable than ordinary single-rail logic circuits. On two-rail logic circuits, path delay faults are always functional sensitizable and may be r obust testable. Even if faults that no codeword input vectors functionally sensitize occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.

“…No previous scan design has focused on TRLCs. Sparmann et al researched the testability of unate gate network [7], [8]. Since TRLCs are unate, their results are applicable to TRLCs.…”

Section: Introductionmentioning

confidence: 99%

Design for Delay Fault Testability of 2-Rail Logic Circuits

Katoh

IEICE Trans. Inf. & Syst.

2009

SUMMARYThis paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and −14.5 percent on average, respectively. key words: 2-rail logic circuits, design for testability, delay fault testing, scan design, set-reset operation