2008 14th IEEE Pacific Rim International Symposium on Dependable Computing 2008
DOI: 10.1109/prdc.2008.8
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Path Delay Fault Test Set for Two-Rail Logic Circuits

Abstract: Two-rail logic circuits can be eciently tested b y non-codeword v e ctor pairs. However, non-codeword vector pairs may sensitize some path delay faults which aect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with non-codeword v e ctor pairs may be over-testing. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the over-testing.

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