Path Delay Fault Test Set for Two-Rail Logic Circuits

Abstract

Two-rail logic circuits can be eciently tested b y non-codeword v e ctor pairs. However, non-codeword vector pairs may sensitize some path delay faults which aect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with non-codeword v e ctor pairs may be over-testing. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the over-testing.