Delay Fault Testability on Two-Rail Logic Circuits

Abstract

The importance o f r edundant technologies for improving dependability and delay fault testability are g r owing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and discusses testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is just twice t h a t i n o r dinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are m o r e testable than ordinary single-rail logic circuits. On two-rail logic circuits, path delay faults are always functional sensitizable and may be r obust testable. Even if faults that no codeword input vectors functionally sensitize occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.

Path Delay Fault Test Set for Two-Rail Logic Circuits

“…So, redundant technologies for improving dependability become increasingly important. Two-rail logic (TRL) circuit design is a well-known class of redundant designs for logic circuits providing strongly fault secure (SFS) property for unidirectional stuck-at faults [4,5,6] 1 . The recent highdensity VLSIs also lead to increasing delay faults caused by manufacturing defects, and so manufacturing testing capable of detecting delay faults is also of increasing signicance [3,7].…”