Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits

Namba, Kazuteru; Ito, Hideo

doi:10.1109/tc.2010.230

Cited by 2 publications

(1 citation statement)

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“…From this reason, a path through the fault should be sensitized for testing the transition delay fault. In path delay fault testing, a signal is an on-input of path p if it is on path p. If a gate g is on path p and an input line of the gate g is not on p, the line is called an off-input of p [1], [17]. A logic value is the controlling value to a gate if it determines the output value of the gate regardless of the values on the other inputs to the gate.…”

Section: Transition Fault and Path Delay Faultmentioning

confidence: 99%

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion

Zhang

Namba

Ito

2014

IEICE Trans. Inf. & Syst.

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SUMMARYWith IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.

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Section: Transition Fault and Path Delay Faultmentioning

confidence: 99%