Mid-frequency delta-I noise analysis of complex computer system boards with multiprocessor modules and verification by measurements

Garben, B.; McAllister, M.F.; Becker, W.D.; Frech, R.

doi:10.1109/6040.938296

Cited by 17 publications

(9 citation statements)

References 5 publications

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“…This is expected from the results in the previous section, and is in contrast to the results reported in Ref. [4] for an actual product MCM-D which has a low inductive thin film top power/ground plane pair and a pin-in hole connector to the board. There, the 'horizontal' resonant loop has only an L-eff of SpH, due to the low plane path inductance, which caused only a minor mid-frequency noise peak, whereas the major noise peak was caused by the 'vertical' resonant loop (down to the nearest board capacitors) with L-eff = 12pH.…”

Section: Introductioncontrasting

confidence: 75%

“…The methodology has been described in detail in Ref. [4] where an IBM product with MCM-D was analyzed. This paper studies the differences between experimental MCM-C (full glass ceramic) and MCM-D (one plane pair thin film at MCM top side) designs.…”

Section: Introductionmentioning

confidence: 99%

“…Power noise simulations are essential in the early development phase of chip and package design. For mid-frequency decoupling optimization the power distribution of the entire package with capacitors and all parasitic inductances must be simulated [3], [4], [SI. In this paper SPEED2000 from Sigrity Inc. has been used for the simulations [6].…”

Section: Introductionmentioning

confidence: 99%

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Package and chip design optimization for mid-frequency power distribution decoupling

Garben

Katopis²,

Becker³

Electrical Performance of Electronic Packaging,

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In this paper the mid-frequency power supply noise has been studied for a complex, next generation computer system by simulations of the complete module and board power distribution system. An MCM-D and MCM-C design and the effectiveness of on-chip and discrete on-module decoupling capacitors have been compared. The impact of delta-I ramping over several cycles and the impact of the continuous background switching and on-chip leakage have been analyzed. Conclusions are presented to optimize the chip and package design. IntroductionIt is of increasing importance to contain the mid-frequency power noise caused by on-chip switching activity variations, because of tighter supply voltage tolerances due to decreasing operating voltage and shorter cycle times, and because of faster and larger current transients due to increasing switching frequency, chip current, and extensive clock gating [ 11, [2]. Therefore low impedance power delivery and optimized decoupling is mandatory. Power noise simulations are essential in the early development phase of chip and package design. For mid-frequency decoupling optimization the

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Section: Introductioncontrasting

confidence: 75%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Package and chip design optimization for mid-frequency power distribution decoupling

Garben

Katopis²,

Becker³

Electrical Performance of Electronic Packaging,

Self Cite

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“…Components that are ignored in our model, such as the on-chip and off-chip d-caps, generally do not respond to variations at the frequencies of interest. More complex models of the powerdistribution network are shown in [6,8,9]; however, the second-order model effectively captures resonant behavior and is widely used [10,9]. We discuss microprocessor resonance in the context of second-order circuit behavior in the resonant loop among the power supply impedance, inductance between the chip and the die, and on-die capacitors.…”

Section: Medium-frequency Resonance Characteristicsmentioning

confidence: 98%

Exploiting Resonant Behavior to Reduce Inductive Noise

Powell

Vijaykumar

2004

SIGARCH Comput. Archit. News

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Inductive noise in high-performance microprocessors is a reliability issue caused by variations in processor current (di/dt) which are converted to supply-voltage glitches by impedances in the power-supply network. Inductive noise has been addressed by using decoupling capacitors to maintain low impedance in the power supply over a wide range of frequencies. However, even well-designed power supplies exhibit (a few) peaks of high impedance at resonant frequencies caused by RLC resonant loops. Previous architectural proposals adjust current variations by controlling instruction fetch and issue, trading off performance and energy for noise reduction. However, the proposals do not consider some conceptual issues and have implementation challenges. The issues include requiring fast response, responding to variations that do not threaten the noise margins, or responding to variations only at the resonant frequency while the range of high impedance extends to a resonance band around the resonant frequency. While previous schemes reduce the magnitude of variations, our proposal, called resonance tuning, changes the frequency of current variations away from the resonance band to a non-resonant frequency to be absorbed by the power supply. Because inductive noise is a resonance problem, resonance tuning reacts only to repeated variations in the resonance band, and not to isolated variations. Reacting after a few repetitions allows more time for the response and reduces unnecessary responses, decreasing performance and energy loss.

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“…Building on or middle frequency noise methodology [5], the model of the module and PCB is built in SpeedXP to perform the time domain simulations. The processor chip delta-I events are simulated using a voltage dependent resistor model [6].…”

Section: B Middle Frequency Noisementioning

confidence: 99%

Deriving voltage tolerance specification for processor circuit design

Zhou¹,

Friedrich²,

Becker³

2011

2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems

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A well defined power supply tolerance specification is very important for designing processor circuits with sufficient performance margin. We introduce a design flow to derive the voltage tolerance specification by including power noise components due to the significant contributors, namely, voltage drop, voltage gradient, middle frequency chip package resonance noise, high frequency simultaneous switching noise (SSN), and voltage regulation module (VRM) tolerance. This method has been serving well for power tolerance specifications of multiple generations of IBM processor designs. However, the methodology needs further refinement to design the off-chip serial interfaces. As the interfaces are increasing in frequency, the voltage levels and swings are minimized to meet the performance criteria of maximizing the data transfer rate per watt.

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Mid-frequency delta-I noise analysis of complex computer system boards with multiprocessor modules and verification by measurements

Cited by 17 publications

References 5 publications

Package and chip design optimization for mid-frequency power distribution decoupling

Package and chip design optimization for mid-frequency power distribution decoupling

Exploiting Resonant Behavior to Reduce Inductive Noise

Deriving voltage tolerance specification for processor circuit design

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