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The ANSYS/Autodyn software was employed to investigate the dynamic responses of foam-filled corrugated core sandwich panels under air blast loading. The panels were assembled from metallic face sheets and corrugated webs, and PVC foam inserts with different filling strategies. To calibrate the proposed numerical model, the simulation results were compared with experimental data reported previously. The response of the panels was also compared with that of the empty (unfilled) sandwich panels. Numerical results show that the fluid–structure interaction effect was dominated by front face regardless of the foam fillers. Foam filling would reduce the level of deformation/failure of front face, but did not always decrease the one of back face. It is found that the blast performance in terms of the plastic deflections of the face sheets can be sorted as the following sequence: fully filled hybrid panel, front side filled hybrid panel, back side filled hybrid panel, and the empty sandwich panel. Investigation into energy absorption characteristic revealed that the front face and core web provided the most contribution on total energy absorption. A reverse order of panels was obtained when the maximization of total energy dissipation was used as the criteria of blast performance.

This paper describes the system packaging and technologies of the IBM System z9e enterprise-class server. The central electronic complex of the system consists of four nodes, each housing a multichip module (MCM) with 16 chips consuming up to 1,200 W. The z9e server doubles the multiprocessor performance of the System z990 by increasing the central processing unit (CPU) configuration and using an internally developed elastic interface to increase interconnect speed on all high-speed buses. In contrast to all previous zSeriest designs, which were running at half of the processor speed, the packaging interconnects on the multichip module run at the same speed as the processor (1.72 GHz). High frequencies and massively parallel connectivity lead to a raw packaging bandwidth of up to 1,764 GB/s between processors and cache within a single frame for a fully configured four-node z9 system.

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