Deriving voltage tolerance specification for processor circuit design

Abstract

A well defined power supply tolerance specification is very important for designing processor circuits with sufficient performance margin. We introduce a design flow to derive the voltage tolerance specification by including power noise components due to the significant contributors, namely, voltage drop, voltage gradient, middle frequency chip package resonance noise, high frequency simultaneous switching noise (SSN), and voltage regulation module (VRM) tolerance. This method has been serving well for power tolerance specifications of multiple generations of IBM processor designs. However, the methodology needs further refinement to design the off-chip serial interfaces. As the interfaces are increasing in frequency, the voltage levels and swings are minimized to meet the performance criteria of maximizing the data transfer rate per watt.