Microarchitectural power modeling techniques for deep sub-micron microprocessors

Kim, Nam Sung; Kgil, Taeho; Bertacco, Valeria; Austin, Todd; Mudge, Trevor

doi:10.1145/1013235.1013290

Cited by 13 publications

(10 citation statements)

References 22 publications

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“…We also performed power simulations of protected and unprotected circuits. Dynamic power was estimated using the procedure in [20], in which the switching capacitance for each node is estimated. This allows the calculation of energy for each transition.…”

Section: Resultsmentioning

confidence: 99%

Time redundant parity for low-cost transient error detection

Palframan

Kim

Lipasti

2011

2011 Design, Automation &Amp; Test in Europe

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Abstract-With shrinking transistor sizes and supply voltages, errors in combinational logic due to radiation particle strikes are on the rise. A broad range of applications will soon require protection from this type of error, requiring an effective and inexpensive solution. Many previously proposed logic protection techniques rely on duplicate logic or latches, incurring high overheads. In this paper, we present a technique for transient error detection using parity trees for power and area efficiency. This approach is highly customizable, allowing adjustment of a number of parameters for optimal error coverage and overhead. We present simulation results comparing our scheme to latch duplication, showing on average greater than 55% savings in area and power overhead for the same error coverage. We also demonstrate adding protection to reach a target logic soft error rate, constituting at best a 59X reduction in the error rate with under 2% power and area overhead.

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Section: Resultsmentioning

confidence: 99%

Time redundant parity for low-cost transient error detection

Palframan

Kim

Lipasti

2011

2011 Design, Automation &Amp; Test in Europe

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“…Energy is estimated using a modified SimPanalyzer ARM simulator [14], which models the effects of internal and external switching and leakage. For Sim-Panalyzer parameters related to power, we use values from a template file provided with SimPanalyzer.…”

Section: Experimental Methodologymentioning

confidence: 99%

A low overhead hardware technique for software integrity and confidentiality

Rogers

Milenković

2007

2007 25th International Conference on Computer Design

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“…The simulator used to evaluate the performance and energy of the proposed architectures is a derivative of the Sim-Panalyzer ARM simulator [28]. Sim-Panalyzer is itself an extension of sim-outorder, the most detailed simulator from the SimpleScalar suite [9].…”

Section: Experimental Environmentmentioning

confidence: 99%