Time redundant parity for low-cost transient error detection

Abstract

Abstract-With shrinking transistor sizes and supply voltages, errors in combinational logic due to radiation particle strikes are on the rise. A broad range of applications will soon require protection from this type of error, requiring an effective and inexpensive solution. Many previously proposed logic protection techniques rely on duplicate logic or latches, incurring high overheads. In this paper, we present a technique for transient error detection using parity trees for power and area efficiency. This approach is highly customizable, allowing adjustment of a number of parameters for optimal error coverage and overhead. We present simulation results comparing our scheme to latch duplication, showing on average greater than 55% savings in area and power overhead for the same error coverage. We also demonstrate adding protection to reach a target logic soft error rate, constituting at best a 59X reduction in the error rate with under 2% power and area overhead.

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic

“…Synchronous CED schemes can be very expensive since they require the storage of all redundant data bits (N or C additional redundant registers in Fig. 1 [20]). Hence, asynchronous CED schemes must include another extra 1-bit register dedicated only to sample their error flags, and so ensuring results at steady state during the necessary time for starting the recovery procedures.…”

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems

“…Hardware redundancy such as TMR is one of the best-known techniques to deal with hard error and to improve manufacturing yield [10,11]. Unfortunately, this architecture is vulnerable to SETs and timing errors, which is the rising issue in advanced CMOS technology nodes [15,16]. One solution is to combine TMR with others techniques such as Razor or Razor II.…”

“…Signals shown in this figure correspond to that presented in In Fig.10, we can observe that error signal turns to logic-1 signaling that vout2 and captured PO have different values during the comparison window. During the same period between t=90ns and t=100ns, CL1 is put in stand-by (stable logic 00000000 16 at i1) while CL3 is turn on (i3 receives captured primary input). The re-configuration successfully finishes before the beginning of new CLK period.…”

“…The re-configuration successfully finishes before the beginning of new CLK period. At next CLK positive edge (t=100ns), the previous value of primary input (33EC884A 16 ) is applied to CL2 and CL3. This shows that the input register and the control logic module have correctly triggered a re-computation.…”

A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies

“…The last cost-effective CED-based solutions [8][9][10] [11] have been devised by using transition detectors. They aim at coping with environmental and manufacturing variability-induced delay faults that cause timing errors, but they are also claimed to mitigate TFs.…”