Methodology of MOSFET characteristics fluctuation description using BSIM3v3 SPICE model for statistical circuit simulations

Azuma, A.; Oishi, A.; Okayama, Y.; Kasai, K.; Toyoshima, Y.

doi:10.1109/iwstm.1998.729756

Cited by 10 publications

(5 citation statements)

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“…The variation of buffer delay originates from the device parameters deviating from their nominal values, as statistically modeled in Zarkesh-Ha et al [1999] and Azuma et al [1998]. The fluctuation of the buffer delay is typically approximated as being linear in the device parameter variations [Sundareswaran et al 2008;Devgan and Kashyap 2003].…”

Section: Buffer Delay Distributionmentioning

confidence: 99%

Effect of process variations in 3D global clock distribution networks

Pavlidis

Micheli

2012

J. Emerg. Technol. Comput. Syst.

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In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered in this article. A statistical clock skew model incorporating both the systematic and random components of process variations is employed to describe this effect. Two regular 3D clock tree topologies are investigated and compared in terms of clock skew variation. The statistical skew model used to describe clock skew variations is verified through Monte-Carlo simulations. The clock skew is shown to change in different ways with the number of planes forming the 3D IC and the clock network architecture. Simulations based on a 45-nm CMOS technology show that the maximum standard deviation of clock skew can vary from 15 ps to 77 ps. Results indicate that simply increasing the number of planes of a 3D IC does not necessarily lead to lower skew variation and higher operating frequencies. A multigroup 3D clock tree topology is proposed to effectively mitigate the variability of clock skew. Tradeoffs between the investigated 3D clock distribution networks and the number of planes comprising a 3D circuit are discussed and related design guidelines are offered. The skew variation in 3D clock trees is also compared with the skew variation of clock grids.

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Section: Buffer Delay Distributionmentioning

confidence: 99%

Effect of process variations in 3D global clock distribution networks

Pavlidis

Micheli

2012

J. Emerg. Technol. Comput. Syst.

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“…Corner analysis is useful for estimating inter-die process variations for 2-D ICs but this method often introduces pessimism in the timing of a circuit. Another method for statistical clock skew analysis based on Monte Carlo simulation is introduced in [14]; the computational time of this method is, however, prohibitively high for large scale ICs. Several statistical skew modeling and timing analysis methods considering intra-die variations are presented in [13,15,16] to efficiently analyze skew variations.…”

Section: Related Workmentioning

confidence: 99%

“…The variation of the buffer delay originates from the device parameters deviating from their nominal values, as statistically modeled in [8,14]. The fluctuation of the buffer delay is typically approximated as being linear to the device parameter variations [16,19].…”

Section: Buffer Delay Distributionmentioning

confidence: 99%

“…Rin and C l of each buffer, therefore, remain approximately the same. For a 3-D clock tree, as described by (14), the σ m W ID (s,k) between two sinks decreases as the number of non- shared clock buffers (e.g., the buffers after the n s,k buffers in Fig. 5 As the number of planes increases, however, both the number of buffers connected to a TSV and the length of TSVs increase.…”

Section: Skew Variation In 3-d Clock Treesmentioning

confidence: 99%

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Process-induced skew variation for scaled 2-D and 3-D ICs

Pavlidis

Micheli

2010

Proceedings of the 12th ACM/IEEE International Workshop on System Level Interconnect Prediction

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Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented at scaled technology nodes and for a 3-D circuit with an increasing number of planes is investigated in this paper. An accurate model used to describe the effect of the proper sources of variations on each of these design approaches is proposed. The distribution of the pair-wise skew variation is obtained for single scaled or multi-plane (not scaled) clock distribution networks. The accuracy of the presented statistical skew model is verified through Monte-Carlo simulations. As shown in this paper, the clock skew variation due to technology scaling and/or die stacking exhibits a considerably different behavior. A comparison between these two design paradigms is offered such that the appropriate technology node and number of planes are selected to produce a low clock skew variation and high operating frequency. A popular global clock tree topology is employed in a planar (2-D) circuit where technology scaling is applied and in a 3-D circuit with an increasing number of planes. For this clock tree topology, the maximum supported clock frequency increases from 2.75 GHz to 3.74 GHz by proper die-stacking at a 90 nm technology node. 3-D integration is shown to be an alternative to reduce skew variation without the need of aggressive technology scaling.

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“…Environmental factors that occur during chip operation include power supply variations and temperature changes across the chip. Physical factors affected during fabrication include various parameters but they are not limited to interconnect line-width [5][6][7], metallic grain size [8][9][10] and transistor channel length [11][12][13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Propagation delay deviations due to process induced line parasitic variations in global VLSI interconnects

Verma

Singh

Kaushik

et al. 2011

2011 IEEE Recent Advances in Intelligent Computational Systems

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Process variation in current nanometer regime has recently emerged as a major concern in the design of very large scale integrated (VLSI) circuits including interconnect. Process variation leads to many uncertainties on circuit performances such as propagation delay. With the shrinking channel dimensions of MOSFET to nanometer scale, the performance of VLSI/ULSI chip becomes less predictable. The predictability of circuit performance may be reduced due to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. The interconnect line resistance and capacitance varies due to changes in interconnect width and thickness, substrate, implant impurity level, and surface charge. This paper presents the variation of propagation delay through driver-interconnect-load (DIL) system due to various effects of interconnect parasitic. The impact of process induced variations on propagation delay of the circuit is discussed for three different fabrication technologies of 130nm, 70nm and 45nm. The comparison between these three technologies extensively shows that the effect of line resistive and capacitive parasitic variations on propagation delay has almost uniform trend as feature size shrinks. However, resistive parasitic variation in global interconnects has very nominal effect on the propagation delay as compared to capacitive parasitic. Propagation delay variation is observed from 0.01% to 0.04% and -4.32% to 18.1% due to resistive and capacitive deviation of -6.1% to 25% respectively.

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Methodology of MOSFET characteristics fluctuation description using BSIM3v3 SPICE model for statistical circuit simulations

Cited by 10 publications

References 0 publications

Effect of process variations in 3D global clock distribution networks

Effect of process variations in 3D global clock distribution networks

Process-induced skew variation for scaled 2-D and 3-D ICs

Propagation delay deviations due to process induced line parasitic variations in global VLSI interconnects

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