Mechanism for Cu void defect on various electroplated film conditions

Reduction of annealed-induced wafer defects in dual-damascene copper interconnects

“…A seed layer with poor step coverage can aggravate the formation of voids during the process of gap filling [3][4][5]. In order to ascertain a smooth and continuous surface morphology of the seed, pre-stress measurement of seed layer was studied before the plating process.…”

“…Higher anneal temperatures are required to stabilize the microstructure by initiating and promoting Cu grain growth. Defects arise gradually due to thermal expansion coefficient mismatch between Cu and its surrounding ultralow k dielectric material and the Si substrate [1][2][3]. Electromigration (EM) and stress migration (SM) reliability strongly depend on post-electrochemical plating (ECP) Cu film grain size, orientation, and intrinsic stress in patterned structures [2].…”

“…Electromigration (EM) and stress migration (SM) reliability strongly depend on post-electrochemical plating (ECP) Cu film grain size, orientation, and intrinsic stress in patterned structures [2]. This can lead to electrical discontinuity through missing metal defect (MMD) (or commonly known as Cu void) indirectly affecting yield process [3]. For copper dual-damascene interconnects two main EM failure modes have been identified, namely the later (strong) mode and the early (weak) mode [1,4].…”

In-Situ Optical Monitoring of Electrochemical Copper Deposition Process for Semiconductor Interconnection Technology

“…Later, Feng and et. al. reported that a ratio of (111)/(200) between the amount of Cu and the impurities in an electroplated Cu film was strongly related to the formation of void defects [5]. They also showed a significantly decreased number of void defects in pulse-reverse current.…”

Stress-Induced Grain Boundary Migration in Polycrystalline Copper

“…19,20 In addition, the grain structures of Cu films can affect the quality of chemical mechanical planarization (CMP); nonuniform grain texturing can lead to irregularities in planarization rates and broad grain size distributions can lead to mechanical failure during CMP. 21 The importance of grain structure on IC performance and reliability motivates considerable interest in understanding its formation and evolution during IC fabrication and operation. In turn, improved understanding of grain structure formation and evolution can lead to IC designs and process protocols that improve product performance and reliability, for example, different chemistries and operating conditions in the electrochemical deposition processes used to deposit Cu lead to different average grain sizes and different impurities in the Cu.…”