Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects

Chiodarelli, Nicolò; Sugiura, Masahiro; Kashiwagi, Yusaku; Li, Yunlong; Arstila, Kai; Richard, Olivier; Cott, Daire; Heyns, Marc; Gendt, Stefan De; Groeseneken, G.; Vereecken, Philippe M.

doi:10.1088/0957-4484/22/8/085302

Cited by 107 publications

(78 citation statements)

References 36 publications

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“…Regarding resistivity, the lowest values reported fall in the range of 0.5 to 1 mΩ.cm, i.e. at least two orders of magnitude higher than the resistivity of aggressively scaled Cu interconnects [65,67,[69][70][71]. These reduced performances can be explained by two main factors: (1) the quality of the CNTs produced by CCVD, which is a relatively lowtemperature process compared to arc-based processes; and (2) the non-ideal packing density of CNTs in integrated interconnects.…”

Section: Transport Properties Of Cntsmentioning

confidence: 93%

A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits

Todri‐Sanial

Ramos

Okuno

et al. 2017

IEEE Circuits Syst. Mag.

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Section: Transport Properties Of Cntsmentioning

confidence: 93%

A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits

Todri‐Sanial

Ramos

Okuno

et al. 2017

IEEE Circuits Syst. Mag.

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“…This requires the low temperature growth of CNT (< 400 °C) using materials and equipment which are considered compatible and scalable to large scale manufacturing. While many examples of CNT test vias have been demonstrated in the literature 7,8,9,10,11,12,13,14 , most of these use Fe as catalyst which is regarded as a contaminant in IC manufacturing 15 . Besides, the growth temperature used in many of these works is much higher than the upper limit of 400 °C.…”

mentioning

confidence: 99%

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Vollebregt

Ishihara

2015

JoVE

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We demonstrate a method for the low temperature growth (350 °C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-κ dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used. Video LinkThe video component of this article can be found at

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“…In recent reports the diffusion barrier TiN is used as conductive material. 11,12,15 Focussing on the application of CNTs for local interconnects, CNT based vias were prepared using Poly-Si as conductive substrate. …”

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confidence: 99%

Distinguishing between Individual Contributions to the Via Resistance in Carbon Nanotubes Based Interconnects

Fiedler

Toader

Hermann

et al. 2012

ECS J. Solid State Sci. Technol.

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We report on the design and fabrication of carbon nanotube (CNT) vias based on a hybrid metal/CNT technology. The CNTs were integrated on a 4 inch Si wafer platform using conventional semiconductor processes. Multiwalled carbon nanotubes were grown vertically aligned on a copper based metal line. Via holes were prepared using a single damascene process. By employing a substratebased selective deactivation of the catalyst, CNT growth was restricted to the vias. Following this process scheme, the impact of post-CNT growth procedures, like chemical mechanical planarization and sample annealing, were investigated and electrically evaluated using conductive atomic force microscopy and current-voltage (I-V) characterization. Probing 440 individual structures, the resistance of two series-connected 5 μm vias were determined to be (800 ± 60) after chemical mechanical planarization. By obtaining the I-V characteristics of single CNTs within an individual via, we found that the measured resistance is determined by the contact resistance of the CNT-metal interface. Two mechanisms were found to be relevant here. First partial oxidation of the metal interface during processing, and secondly, stress-induced voiding caused by the high temperatures during the CNT growth process. Changes in the integration scheme to reduce the overall CNT via resistance are proposed. Continuous down-scaling of the interconnect structures in ultralarge-scale-integrated electronic devices causes deterioration of the resistivity and reliability of copper lines. The International Technology Roadmap for Semiconductors (ITRS) proposed several emerging technologies to replace copper in future interconnect schemes.1 Among them, carbon nanotubes (CNT) are very promising due to their extraordinary electrical properties.2,3 Also the thermal properties of CNTs are highly beneficial for interconnect applications. Due to their one dimensional nature the thermal conduction is anisotropic with a longitudinal thermal conductivity, which can be as large as 6000 W/mK. [4][5][6] Furthermore, due to the strong sp 2 hybridized carbon bonds the CNTs exhibit an extraordinary mechanical strength leading to a large current carrying capacity, which can reach values three orders of magnitude higher than copper. [1][2][3] Currently research of CNT interconnects focuses on vias.7-18 Main challenges hereby are the compatibility with the Back-end-of-the-line (BEOL) technology requirement, 7 while simultaneously a high CNT quality and a large CNT density is required. 17 Various substrate materials for CNT growth are used by different groups. In recent reports the diffusion barrier TiN is used as conductive material. 11,12,15 Focussing on the application of CNTs for local interconnects, CNT based vias were prepared using Poly-Si as conductive substrate. 8Also CNT growth behavior on unstructured samples was investigated using Ta as substrate material, which is a typical liner material in BEOL. 19,20 Besides this work, the group of Awano, 10,13,18 incorporates a Cu line in conjunc...

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Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects

Cited by 107 publications

References 36 publications

A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits

A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits

Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Distinguishing between Individual Contributions to the Via Resistance in Carbon Nanotubes Based Interconnects

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