Fabrication of Low Temperature Carbon Nanotube Vertical Interconnects Compatible with Semiconductor Technology

Abstract

We demonstrate a method for the low temperature growth (350 °C) of vertically-aligned carbon nanotubes (CNT) bundles on electrically conductive thin-films. Due to the low growth temperature, the process allows integration with modern low-κ dielectrics and some flexible substrates. The process is compatible with standard semiconductor fabrication, and a method for the fabrication of electrical 4-point probe test structures for vertical interconnect test structures is presented. Using scanning electron microscopy the morphology of the CNT bundles is investigated, which demonstrates vertical alignment of the CNT and can be used to tune the CNT growth time. With Raman spectroscopy the crystallinity of the CNT is investigated. It was found that the CNT have many defects, due to the low growth temperature. The electrical current-voltage measurements of the test vertical interconnects displays a linear response, indicating good ohmic contact was achieved between the CNT bundle and the top and bottom metal electrodes. The obtained resistivities of the CNT bundle are among the average values in the literature, while a record-low CNT growth temperature was used. Video LinkThe video component of this article can be found at

Impact of Temperature on Structure Deformation for Monolithic Inter-Tier vias In Monolithic 3D IC Packaging System

“…26 The process of growing vertically-aligned CNT bundles on electrically conductive thin-films at low temperature of 350 °C was illustrated in Ref. 27. It is amicable with the conventional semiconductor fabrication.…”