Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA

Libous, J.; O’Connor, Daniel

doi:10.1109/96.618226

Cited by 37 publications

(6 citation statements)

References 5 publications

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“…The resulted circuits have a huge number of RLC elements, and model reduction [3], [4] or some other simplification techniques [5], [6] are needed to reduce the model complexity. However, the computational cost still remains high, limiting the application of the method.…”

Section: B Board and Package Modelingmentioning

confidence: 99%

Modeling and design for beyond-the-die power integrity

Shi

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Power integrity gains growing importance for integrated circuits in 45nm technology and beyond. This paper provides a tutorial of modeling and design for beyond the die power integrity.We explain the background of simultaneous switching noise (SSN) and its impacts on circuit designs. We discuss various models of different accuracy and complexity for the board, package and chip, and suggest how to select proper ones for board-package-chip co-simulation and co-design of SSN. We then review different design techniques to suppress SSN, including I/O planning and placement, decoupling capacitor allocation, package layer stacking and power/ground plane stapling.

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Section: B Board and Package Modelingmentioning

confidence: 99%

Modeling and design for beyond-the-die power integrity

Shi

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Input-only clocks and enable signals were brought in the center of the bank, making the total number of cells in a bank 44. In contrast to the test chip in [7], the IO's are not arranged in the traditional ring pattern around the perimeter of the die. Fig.…”

Section: A Measurement Structuresmentioning

confidence: 99%

“…The fact that position does strongly impact the amount of SSO noise coupled to the quiet output raises the question of how much the selection of another quiet output would have affected the results. Unfortunately, our initial test board was not designed to carry out the detailed measurements of [7]. Data from that study suggest that SSO noise is maximized near the center of the switching structure, and that moving slightly away from this region could cause differences of as much as 30%.…”

Section: Effect Of Position and Number Of Io Switchingmentioning

confidence: 99%

Electrical evaluation of flip-chip package alternatives for next generation microprocessors

Darnauer

Chengson

Schmidt³

et al. 1999

IEEE Trans. Adv. Packag.

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Two styles of flip-chip packages for next-generation microprocessors were designed: a low-cost organic ball-gridarray (BGA) and a thin-film-on-ceramic land-grid array (LGA). Simultaneous switching output (SSO) noise, and core noise were measured. Although SSO was improved by a factor of two over the previous generation of packaging, core noise was still quite significant. We found that core noise is best managed by placing low-inductance capacitance close to the noise source, i.e., using on-chip capacitors, coupled planes in the package, or on-package bypass capacitors. Because of the lower impedance of its power planes, the ceramic package showed significantly better electrical performance than the organic. Addition of on-package bypass capacitors greatly narrows the gap between the two packages.Index Terms-Circuit noise, flip-chip devices, integrated circuit packaging, plastic packaging, thin-film circuit packaging, time domain measurements.

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“…The ASIC chip camer used in this study, would require more than 50,000 elements to model once the design file is translated into L3D input format. Therefore, from symmetry arguments, the choice is made to model only a quadrant of the package [5]. Given the design displays symmetry about the x-and y-axes, a quadrant inductance model should be representative of the entire package.…”

Section: Application Descriptionmentioning

confidence: 99%

“…The loop' indu! :tance .of the physical system is computed using an IBM tool,' L3D [4,5,6,7]. Quasi-static inductance is computed by.…”

Section: A Inductance Modeling Bakkgroundmentioning

confidence: 99%

Effect of organic package core via pitch reduction on power distribution performance

Audet

O’Connor

Grinberg

et al.

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)

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power distribution structure, and iii) overall module cost and ! ~~~~ ~ Advances in CMOS technology continue to provide performance.can be further reduced for vo limited flin-chin (c4, ,,ad increased circuit density and performance at a lower Cost. Die core via impact On a 214i2 structure having size and 212,300 and 375um core via pitches for various signal counts will be examined. The power distribution figure of merit based bv shrinking the area on different core via pitches, number of build up layers and.. pitch. These advances continue to drive package ground rule improvements to eficiently distribute signal and power reducing Cost, One such groundrule for organic build-up presented. The number Of rows (si@a1 count) wired Out is performance comparison, for a specific application, to optimize both the chip size and the package layer'count for the best module cost and performance IS also considered. Background: Buildup Technology Descriptionpackages is the core via pitch. Core via pitch reduction can significantly improve the package power distribution and buildup , signal escape. This paper presents the package design tradeoffs for core via pitch reduction to support a 90nm 9.3mm ASIC die using a m u m full area array C4 pitch. The impactThe sequential Buildup chip carrier technology starts with of core via pitch on Power distribution P e r f m u " an FR4 or BT printed wiring board with plated through boles wireability, and cost will be presented, including electrical (PTH) [2,3]. Those PTH's will be called core vias. A liquid or modeling and simulation results. Design trade-offs to optimize dry film dielectric is applied Over the surface, and micro vias both the chip and package are presented, including die C4 pad to the layer directly below are formed by laser or pitch and depth versus module cost and performance photolithography processes, followed by subtractive or 1. lntrnductinn additive plating processes to form the circuitry. These steps ~ ~~~.~ .__.... ~~ can be repeated as many times as needed. The buildup via Process can Provide large numbers of small blind and buried packaging solution that will meet stringent electrical vias economically, consuming far less real estate than normal Electronic core vias. The blind vias of the buildup technology are much Today the semiconductor industry is faced with the difficult challenge of developing a effective eleckonic of high Derformance SvStemS. smaller than core via (PTHs). -. packaging suppliers continue to aggressively invest in the development of advanced groundrules. This is required to stay build UP layers on both side are competitive and meet challenges driven by the same for mechanical reasons and are represented by the advancements in the semiconductor indusm. The 2003 term x-y-x, where X represents the number of buildup layersInternational Technology Roadmap for Semiconductors [ 11 and y the number of core layers. The 2-4-2 sequential buildup predicts a rapid reduction in the flip chip pad pitch, This puts carrier is f "ed by W O build UP layers on...

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Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA

Cited by 37 publications

References 5 publications

Modeling and design for beyond-the-die power integrity

Modeling and design for beyond-the-die power integrity

Electrical evaluation of flip-chip package alternatives for next generation microprocessors

Effect of organic package core via pitch reduction on power distribution performance

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