Abstract-The power consumption of microprocessors isincreasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.

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In this paper a modeling methodology using spline functions with finite time difference is proposed for modeling digital U 0 drivers. Digital driver circuits can be accurately modeled using their static characteristics for normal excitations, but for faster excitations static characteristic models tend to lose their accuracy as the dynamic characteristics start to dominate the static characteristics. Spline function with finite time difference modeling includes previous time instances to capture dynamic characteristics for accurate modeling of digital drivers. In this paper the speed and accuracy of the proposed method is analyzed and compared with Radial Basis Function (RBF) modeling for different test cases.

In this paper, power supply noise is modeled accurately using eficient macro-models of non-linear digital drivers. Spline function with $&e time difference approximation modeling technique takes into account both the static and the dynamic memory characteristics of the driver during modeling. For power supply noise analysis, the above method has been atended to multiple ports by taking the previous time instances of the power supply voltage/current into account. The method discussed can be used to capture sensitive effects like Simultaneous Switching Noise (SSN) and cross talk accurately, when multiple drivers are switching simulta~ous(y. A comparison study between the presented method and the transistor level driver models indicate a computational speed-up in the range of 10-40 with an error of less than 5%. For highly non-linear drivers, a method based on Artificial Neural Networks (ANN) is briefly discussed to capture SSN.

This paper presents the simultaneous switching noise (SSN) measurements, modeling, and simulation of a flip-chip complementary metal-oxide-semiconductor (CMOS) applicationspecific integrated circuit (ASIC) test chip on a multilayer ceramic ball grid array (CBGA) package. Technology and design features of the chip and package test vehicles are described. Timedomain noise measurement techniques and results are presented in detail. Circuit modeling and simulation methodologies are developed and validated by strong correlation between measurement and simulation results.