Measurement method for transient programming current of 1T1R phase-change memory

Kurotsuchi, Kenzo; Takaura, N.; Matsuzaki, N.; Matsui, Yasuhiro; Tonomura, Osamu; Fujisaki, Yasumasa; Kitai, N.; Takemura, Riichiro; Osada, Kensuke; Hanzawa, S.; Moriya, Hideshige; Iwasaki, Takaya; Kawahara, Takayuki; Terao, Motoyasu; Matsuoka, M.; Moniwa, Masahiro

doi:10.1109/icmts.2006.1614272

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Cited by 4 publications

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“…Transient reset current is measured by test structure with internal node (inset)(3). Width of reset pulse was 100 ns.…”

mentioning

confidence: 99%

Ta2O5 Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories

Matsui

Kurotsuchi

Tonomura

et al. 2006

2006 International Electron Devices Meeting

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A novel memory cell for phase-change memories (PCMs) that enables low-power operation has been developed. Power (i.e., current and voltage) for the cell is significantly reduced by inserting a very thin Ta 2 O 5 film between GeSbTe (GST) and a W plug. The Ta 2 O 5 interfacial layer works not only as a heat insulator enabling effective heat generation in GST but also as an adhesion layer between GST and SiO 2 underneath. Nonetheless, sufficient current flows through the interfacial layer due to direct tunneling. A low programming power of 1.5 V/100 µA can therefore be obtained even on a W plug with a diameter of 180 nm fabricated using standard 0.13-µm CMOS technology. In addition, the uniformity and repeatability of cell resistance are excellent because of the inherently stable Ta 2 O 5 film properties.

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“…Transient reset current is measured by test structure with internal node (inset)(3). Width of reset pulse was 100 ns.…”

mentioning

confidence: 99%