MATIA: A Programmable 80&amp;lt;tex&amp;gt;$mu$&amp;lt;/tex&amp;gt;W/frame CMOS Block Matrix Transform Imager Architecture

Bandyopadhyay, Abhishek; Lee, Jung Won; Robucci, Ryan; Hasler, P.

doi:10.1109/jssc.2005.864115

Cited by 48 publications

(25 citation statements)

References 21 publications

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“…VMM is an extremely efficient operation when performed in the analog domain [7], [8]. Because this computation is such a "killer app" for modern analog computation, we took special consideration to facilitate their large-scale design in the RASP 2.9v.…”

Section: Vmm Cabmentioning

confidence: 99%

A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing

Schlottmann

Shapero

Nease

et al. 2012

IEEE J. Solid-State Circuits

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We present a field-programmable analog array designed for accurate low-power mixed-signal computation. This 25-mm 350 nm-CMOS reconfigurable analog IC incorporates digital enhancements to increase compatibility in embedded mixed-signal systems. The chip contains 78 computational analog blocks (CABs) which house a variety of processing elements. There are 36 general CABs with hundreds of common analog primitives for computation, 18 digital-to-analog converter (DAC) CABs, each with 8-b compilable DAC capabilities, and 24 vector-matrix multiplier CABs, for low-power parallel processing. A floating-gate routing matrix connects these analog elements to one another, both within individual CABs and between CABs. To facilitate digital interfacing and dynamic reconfigurability, we included a novel network of volatile switches based on digital shift and select registers that control analog switches. These dynamically controlled switches span all of the rows and columns of the internal routing, allowing for run-time system modification and scanning I/O. The digital registers can also double as on-chip memory. We introduce a new hybrid floating-gate switch matrix, which includes switches that eliminate previously observed mismatch issues to provide highly precise computation. To highlight the potential of this digitally enhanced analog processor, we demonstrate a dynamically reconfigurable image transformer, an arbitrary waveform generator, and a mixed-signal FIR filter.Index Terms-Analog signal processing, field-programmable analog array (FPAA), rapid analog prototyping, vector-matrix multiplier (VMM). I. ANALOG RECONFIGURABILITYA S monolithic integration of analog and digital circuitry pervades the market, integrated circuit designers are faced with the increasingly difficult task of verifying complex mixedsignal systems. The most common approach for this task is to simulate the analog subsystem, fabricate and test the mixedsignal system, and then repeat [1]. We propose that a faster and more efficient approach is to prototype mixed-signal systems using reconfigurable analog hardware, similar to the common strategy of using FPGAs to prototype digital systems.In addition to simple prototyping, reconfigurable analog systems are extremely powerful for embedded computing applications, acting as coprocessors. Analog signal processing (ASP) Manuscript Fig. 1. Architecture and layout of the RASP 2.9v FPAA. (a) The system-level diagram shows the analog core and surrounding digital control and interfacing. The analog processor communicates directly with the microcontroller via an SPI interface. A complete software tool chain is available for analog synthesis in Simulink and connects to the hardware platform with USB. (b) The RASP 2.9v IC was fabricated in 350-nm CMOS and consumes 25 mm of area. systems can easily utilize subthreshold transistor operation to perform ultra low-power computation, especially in parallel computing systems [2].We present the RASP 2.9v (Fig. 1), which is the next generation of field-programmable analog ar...

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Section: Vmm Cabmentioning

confidence: 99%

A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing

Schlottmann

Shapero

Nease

et al. 2012

IEEE J. Solid-State Circuits

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“…Integrating non-volatile analog memory and a versatile random access approach allows a variety of behaviors like multi-resolution and selective sensing. This work advances the circuit designs and concepts in previous work [6], which implemented a block transform imager system. In particular, advancements were made amongst the low-level circuit topologies, including current sensing circuits, pixel structure, and the analog memory, along with the choice of the vector matrix multiplier design.…”

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confidence: 84%

“…The programming procedure inherently avoids issues of voltage offsets due to mismatches in the transistors and in the op amp itself by directly monitoring the output in the programming cycle. [6] discusses the use of FGPFETs, which act much like PFETS that have a programmable threshold voltage offset. Generating 16 differential outputs requires 32 amplifier structures.…”

Section: Random Access Analog Memorymentioning

confidence: 99%

A 256×256 separable transform CMOS imager

Robucci

Gray

Abramson

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper discusses a 256x256 computational imager capable of performing separable transforms. Unlike traditional imagers, this imager performs computation on-chip and inpixel. The primary computation performed is a separable matrix transformation. Several developments were made since a previous matrix transform imager to expand functionality and resolution. New circuit design emphasized dynamic range, accuracy, and speed. This architecture includes a novel overlapping block scheme allowing 8x8 general separable 2-D convolutions as well as 16x16 block transforms.Modern CMOS imagers are opening a new field of possibilities for combining image sensing and processing. CCD based image sensors previously dominated the camera market, producing high-quality results, but they have the limitation of needing special processes that do not allow for high levels of on-chip integration. Also, CCDs require high voltage generation and consume higher power than CMOS imagers. CMOS imaging technology, on the other hand, can be implemented on standard, relatively low-cost CMOS processes. By integrating circuit components into the image sensor, such as in-pixel ADC's [1], CMOS technology has become competitive in the high-end camera market. Other aggressive circuit integrations in CMOS imaging technology provide additional computationally significant gains, such as random image access [2], dynamic field of view capabilities [3], multi-resolution image sensing [4], and biologically inspired abilities such as edge enhancement [5].Our computational image sensor approach aims to implement many of the aforementioned features in a reconfigurable platform. By integrating focal-plane computation with peripheral analog computation circuitry, a variety of linear transformations can be performed. Integrating non-volatile analog memory and a versatile random access approach allows a variety of behaviors like multi-resolution and selective sensing. This work advances the circuit designs and concepts in previous work [6], which implemented a block transform imager system. In particular, advancements were made amongst the low-level circuit topologies, including current sensing circuits, pixel structure, and the analog memory, along with the choice of the vector matrix multiplier design. The components were designed to target support for larger imagers.

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“…Many sensors report traditional compression methods based on discrete cosine transform (DCT) and discrete wavelet transform (DWT). Although performing DCT and DWT is mainly reported on very small pixel arrays due to high hardware complexity, a few designs report successful compression on larger arrays (see [1] and [2]). Using alternate scanning patterns, such as the Z-curve or Hilbert curve [3], followed by quadtree decomposition results in the compressive image acquisition schemes presented in [4], [5], and [6].…”

Section: Introductionmentioning

confidence: 99%

Compressive image acquisition in modern CMOS IC design

Katic

Kamal

Schmid

et al. 2013

Circuit Theory & Apps

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SUMMARYCompressive sampling (CS) offers bandwidth, power, and memory size reduction compared to conventional (Nyquist) sampling. These are very attractive features for the design of modern complementary metal-oxide semiconductor (CMOS) image sensors, cameras, and camera systems. However, very few integrated circuit (IC) designs based on CS exist because of the missing link between the well-established CS theory on one side, and the practical aspects/effects related to physical IC design on the other side. This paper focuses on the application of compressed image acquisition in CMOS image sensor integrated circuit design. A new CS scheme is proposed, which is suited for hardware implementation in CMOS IC design. All the main physical non-idealities are explained and carefully modeled. Their influences on the acquired image quality are analyzed in the general case and quantified for the case of the proposed CS scheme. The presented methodology can also be used for different CS schemes and as a general guideline in future CS based CMOS image sensor designs.

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MATIA: A Programmable 80<tex>$mu$</tex>W/frame CMOS Block Matrix Transform Imager Architecture

Cited by 48 publications

References 21 publications

A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing

A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing

A 256×256 separable transform CMOS imager

Compressive image acquisition in modern CMOS IC design

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