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We present a single-chip array of 100 biologically-based electronic neuron models interconnected to each other and the outside environment through 30,000 synapses. The chip was fabricated in a standard 350 nm CMOS IC process. Our approach used dense circuit models of synaptic behavior, including biological computation and learning, as well as transistor channel models. We use Address-Event Representation (AER) spike communication for inputs and outputs to this IC. We present the IC architecture and infrastructure, including IC chip, configuration tools, and testing platform. We present measurement of small network of neurons, measurement of STDP neuron dynamics, and measurement from a compiled spiking neuron WTA topology, all compiled into this IC.

We present a field-programmable analog array designed for accurate low-power mixed-signal computation. This 25-mm 350 nm-CMOS reconfigurable analog IC incorporates digital enhancements to increase compatibility in embedded mixed-signal systems. The chip contains 78 computational analog blocks (CABs) which house a variety of processing elements. There are 36 general CABs with hundreds of common analog primitives for computation, 18 digital-to-analog converter (DAC) CABs, each with 8-b compilable DAC capabilities, and 24 vector-matrix multiplier CABs, for low-power parallel processing. A floating-gate routing matrix connects these analog elements to one another, both within individual CABs and between CABs. To facilitate digital interfacing and dynamic reconfigurability, we included a novel network of volatile switches based on digital shift and select registers that control analog switches. These dynamically controlled switches span all of the rows and columns of the internal routing, allowing for run-time system modification and scanning I/O. The digital registers can also double as on-chip memory. We introduce a new hybrid floating-gate switch matrix, which includes switches that eliminate previously observed mismatch issues to provide highly precise computation. To highlight the potential of this digitally enhanced analog processor, we demonstrate a dynamically reconfigurable image transformer, an arbitrary waveform generator, and a mixed-signal FIR filter.Index Terms-Analog signal processing, field-programmable analog array (FPAA), rapid analog prototyping, vector-matrix multiplier (VMM). I. ANALOG RECONFIGURABILITYA S monolithic integration of analog and digital circuitry pervades the market, integrated circuit designers are faced with the increasingly difficult task of verifying complex mixedsignal systems. The most common approach for this task is to simulate the analog subsystem, fabricate and test the mixedsignal system, and then repeat [1]. We propose that a faster and more efficient approach is to prototype mixed-signal systems using reconfigurable analog hardware, similar to the common strategy of using FPGAs to prototype digital systems.In addition to simple prototyping, reconfigurable analog systems are extremely powerful for embedded computing applications, acting as coprocessors. Analog signal processing (ASP) Manuscript Fig. 1. Architecture and layout of the RASP 2.9v FPAA. (a) The system-level diagram shows the analog core and surrounding digital control and interfacing. The analog processor communicates directly with the microcontroller via an SPI interface. A complete software tool chain is available for analog synthesis in Simulink and connects to the hardware platform with USB. (b) The RASP 2.9v IC was fabricated in 350-nm CMOS and consumes 25 mm of area. systems can easily utilize subthreshold transistor operation to perform ultra low-power computation, especially in parallel computing systems [2].We present the RASP 2.9v (Fig. 1), which is the next generation of field-programmable analog ar...

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