In most reconfigurable systems, such as FPAAs and FPGAs, the switch element and its associated memory cell is a necessary overhead for performing computation with the active components. However, floating gate based switches in large-scale FPAAs can be programmed anywhere between simple "off" and "on" connections, which allows these programmable conductances to be used as computational elements within synthesized circuits. This decreases the notion of switches as computational dead weight and increases the potential computational area efficiency within FPAAs.
I. RECONFIGURABLE SYSTEMS AND SWITCHESReconfigurable devices, such as FPGAs and FPAAs, enable the rapid synthesis and development of complex systems without long fabrication cycles. However, the flexibility of these systems generally requires a significant area overhead for the numerous switches and the memory cells that control them, which are used to interconnect the computational components. For digital devices, such as FPGAs, this area overhead can easily consume 60% to 90% of the chip [1], [2]. FPAAs, such as the RASP 2.7 depicted in Fig. 1, have similar or sometimes smaller routing areas. Although these switches are required to provide reconfigurability, they are computational dead weight. However, the floating gate transistor switches of the large-scale FPAA discussed in [3] provide a way to utilize some of this dead weight.The key technology enabling reconfigurability in these Fig. 1. RASP 2.7 die photograph. The window-like rectangles are the computational elements, and the areas in between are composed of routing switches. Memory Element (a) V tun (b) Fig. 2. FPAA switching elements.large-scale FPAAs is the floating gate transistor. Several designs implement reconfigurability through programmable circuit topologies, such as the G M cells of [4], which avoid switch overhead but generally incur other area penalties in the form of redundant computational components. Reconfigurability is commonly achieved using a transmission gate switch, as depicted in Fig. 2a. A memory cell, such as an SRAM, controls the transmission gate which connects a row and column within the routing network. Since the memory cell is digital, the switch can only operate between two states, "on" and "off". However, the floating gate transistor, depicted in Fig. 2b, provides a combined switch and memory cell capable of any arbitrary state between "on" and "off". Using these additional states, many useful circuits can be synthesized within the switch fabric.
II. FLOATING GATE TRANSISTOR SWITCHESThe floating gate switch is simply a pFET with capacitive gate coupling, as shown in Fig. 3. A double poly capacitor is used to couple a control voltage, V C , to the floating gate, and a MOS capacitor is used as a tunneling junction. With no DC path to a fixed potential, charge can be stored on the floating node. The current flowing through the floating gate pFET is then controlled by the voltages coupled onto the floating gate and the amount of charge stored on the floating node. By modifyi...