Compressive sensing on a CMOS separable transform image sensor

Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors

“…For the ADC, it is now dependent on signal resolution instead of measurement resolution and samples at the Nyquist rate such that: (20) Similarly for the amplifier, the noise constraint on the amplifier is now only determined by the quantization noise of the ADC such that (21) with the same assumptions regarding and NEF as before. 12 The wires for the accumulator bank are all local and as such are lumped in with the parasitic portion of the LE delay model.…”

“…Thus, for any alternative compression scheme to be competitive with CS in terms of power, the storage requirements must be on the order of 1000 flip-flops 19 or less. In the case of LZW, the example just described consumes only 3 k storage elements for the coded output, but the corresponding dictionary needed to generate that output code requires an 11 k memory 20 where the storage requirements for both the output code and dictionary increase as higher compression is desired. Even without accounting for differences in computational complexity (which favors CS), the CS compression system, though lossy, offers 6X higher compression at over 10X lower implementation (storage/ power) cost.…”

“…Thus, for CS to be a practical solution for wireless sensor nodes, an energy efficient hardware implementation of the encoder must be realized. Given the relative immaturity of the field, there have been few works that discuss the tradeoffs or costs of realizing CS in hardware [18]- [20] and even fewer measured results [20].…”

Characterization of a compressive imaging system using laboratory and natural light scenes

“…Even faster acquisition could be achieved, and dynamic range improved, by multiplexing parts of the spatially filtered signals onto multiple parallel detectors, as proposed by Ke et al [22], providing a continuum between conventional focal planes and compressive imagers. In the longer term, ASIC image sensors with high pixel counts and programmable on-chip signal aggregation will be able to integrate the pattern encoding directly into the image sensor itself, eliminating the need for an external SLM and enabling CI systems to function with high-performance image formation optics [17,18]. Finally, the most significant performance improvement in CI will be enabled by making use of the intrinsic architectural flexibility for featurespecific imaging [23,24], including face recognition [25,26], to dramatically decrease the basis set size required to acquire a conclusive measurement.…”

“…The basis projections can be sampled by imaging the scene onto the spatial light modulator (SLM), then condensing the resulting energy onto a single detector (optical summing). Alternatively, a 2D array image sensor with spatially weighted sensitivity and analog summing could implement the same operation (electronic summing) [17,18]. Creating an image sensor (focal plane array) that can directly operate as a compressive imager is possible; however, fabricating one with high resolution, optical fill-factor, and sensitivity is challenging, while high resolution SLMs are commercially available.…”