A 256×256 separable transform CMOS imager

Abstract

This paper discusses a 256x256 computational imager capable of performing separable transforms. Unlike traditional imagers, this imager performs computation on-chip and inpixel. The primary computation performed is a separable matrix transformation. Several developments were made since a previous matrix transform imager to expand functionality and resolution. New circuit design emphasized dynamic range, accuracy, and speed. This architecture includes a novel overlapping block scheme allowing 8x8 general separable 2-D convolutions as well as 16x16 block transforms.Modern CMOS imagers are opening a new field of possibilities for combining image sensing and processing. CCD based image sensors previously dominated the camera market, producing high-quality results, but they have the limitation of needing special processes that do not allow for high levels of on-chip integration. Also, CCDs require high voltage generation and consume higher power than CMOS imagers. CMOS imaging technology, on the other hand, can be implemented on standard, relatively low-cost CMOS processes. By integrating circuit components into the image sensor, such as in-pixel ADC's [1], CMOS technology has become competitive in the high-end camera market. Other aggressive circuit integrations in CMOS imaging technology provide additional computationally significant gains, such as random image access [2], dynamic field of view capabilities [3], multi-resolution image sensing [4], and biologically inspired abilities such as edge enhancement [5].Our computational image sensor approach aims to implement many of the aforementioned features in a reconfigurable platform. By integrating focal-plane computation with peripheral analog computation circuitry, a variety of linear transformations can be performed. Integrating non-volatile analog memory and a versatile random access approach allows a variety of behaviors like multi-resolution and selective sensing. This work advances the circuit designs and concepts in previous work [6], which implemented a block transform imager system. In particular, advancements were made amongst the low-level circuit topologies, including current sensing circuits, pixel structure, and the analog memory, along with the choice of the vector matrix multiplier design. The components were designed to target support for larger imagers.