Materials and Device Reliability in SONOS Memories

Ramkumar, K.

doi:10.1007/978-3-319-48705-2_1

Cited by 6 publications

(4 citation statements)

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“…The charge trapping in thin dielectric films has been intensively investigated recently in order to employ this phenomenon in the non-volatile memories as a replacement of the existing floating gate technology [ 1 , 2 , 3 , 4 , 5 , 6 , 7 ]. The charge trapping memory (CTM) design has a lot in common with the floating gate design.…”

Section: Introductionmentioning

confidence: 99%

“…The charge trapping memory (CTM) design has a lot in common with the floating gate design. The main difference is that the CTM concept uses charge storage in spatially separated charge traps in dedicated dielectric layers while the floating gate concept relies on keeping charges in a potential well realized through a poly-Si layer (floating gate) sandwiched between two dielectrics [ 6 ]. The CTM concept is not new but offers some advantages over the floating gate design that are vital for the continuing scaling of non-volatile memories [ 7 ].…”

Section: Introductionmentioning

confidence: 99%

“…The introduction of high- k dielectrics in microelectronic technology boosted CTM development as these dielectrics have been proven to possess large densities of traps whose parameters could be tailored by the fabrication processes and consequent treatments. On the other hand, they could be optimized to satisfy the requirements for replacement of SiO 2 in the nanosized field effect transistors [ 6 , 7 ]. Among the available high- k materials, HfO 2 takes a special place since it is already implemented in real production technologies.…”

Section: Introductionmentioning

confidence: 99%

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Radiation Tolerance and Charge Trapping Enhancement of ALD HfO2/Al2O3 Nanolaminated Dielectrics

et al. 2021

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High-k dielectric stacks are regarded as a promising information storage media in the Charge Trapping Non-Volatile Memories, which are the most viable alternative to the standard floating gate memory technology. The implementation of high-k materials in real devices requires (among the other investigations) estimation of their radiation hardness. Here we report the effect of gamma radiation (60Co source, doses of 10 and 10 kGy) on dielectric properties, memory windows, leakage currents and retention characteristics of nanolaminated HfO2/Al2O3 stacks obtained by atomic layer deposition and its relationship with post-deposition annealing in oxygen and nitrogen ambient. The results reveal that depending on the dose, either increase or reduction of all kinds of electrically active defects (i.e., initial oxide charge, fast and slow interface states) can be observed. Radiation generates oxide charges with a different sign in O2 and N2 annealed stacks. The results clearly demonstrate a substantial increase in memory windows of the as-grown and oxygen treated stacks resulting from enhancement of the electron trapping. The leakage currents and the retention times of O2 annealed stacks are not deteriorated by irradiation, hence these stacks have high radiation tolerance.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Radiation Tolerance and Charge Trapping Enhancement of ALD HfO2/Al2O3 Nanolaminated Dielectrics

et al. 2021

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“…Researchers have reported numerous approaches which use nanoparticles for FG layer prepared by sol-gel method [14] and physical vapor deposition (PVD) [15,16]. However, none of these methods are suitable to control the size, shape and nearestneighbor distance (NND) of NPs simultaneously, which is the crucial requirement of an ideal nanoparticle FG memory device [17]. It is also known that, the low controllability of the areal density and positions of NPs have limited the performance of the memory device applications [13,18].…”

Section: Introductionmentioning

confidence: 99%

Well-ordered nanoparticle arrays for floating gate memory applications

Kuruoğlu¹,

Çalışkan²,

Serin³

et al. 2020

Nanotechnology

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A non-volatile floating gate memory device containing well-ordered Au nanoparticles (NPs) is fabricated as a metal–oxide–semiconductor capacitor structure. With superior control on the size, shape and position of nanoparticles, the presented nano-floating gate memory (NFGM) device possesses almost perfect precision of device geometry. The well-ordered Au NPs embedded within the memory device exhibit large memory window at low operation voltages (8.8V @ ± 15V), fast operation time (<10−4 s) and good retention (up to 107 s). In this work, the structural properties of the NFGM device are correlated with the examined electrical properties. The current results are compared with the other studies in the literature to emphasis the advantages of the precise ordering and geometry of the NPs.

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