Radiation Tolerance and Charge Trapping Enhancement of ALD HfO2/Al2O3 Nanolaminated Dielectrics

Spassov, D.; Paskaleva, A.; Guziewicz, E.; Davidović, V.; Stanković, S.; Djorić-Veljković, S.; Ivanov, Tsvetan; Stanchev, Todor; Stojadinović, N.

doi:10.3390/ma14040849

Cited by 8 publications

(5 citation statements)

References 55 publications

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“…In particular, the tunneling oxide will be more seriously damaged with more programming and erasing sequences, resulting in more charge leakage [ 15 ]. In order to overcome the issue of charge leakage, many device structures have been proposed, e.g., SONOS, BE-SONOS, TAHOS and 3D FLASH [ 6 , 17 , 18 , 19 , 20 ]. The 3D NAND FLASH structure was proposed as a solution when 2D NAND FLASH reached the scaling limit of a 15 nm process node [ 21 ].…”

Section: Introductionmentioning

confidence: 99%

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

et al. 2022

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To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure.

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Section: Introductionmentioning

confidence: 99%

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

et al. 2022

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“…Annealing in an oxygen ambient most strongly affects the charge storage ability of the stacks by increasing the number of trapped electrons and improving the stability of the stacks to a high electric field. Moreover, we have shown that Al 2 O 3 /HfO 2 stacks after RTA in O 2 are radiation-tolerant and their charge storage characteristics are not deteriorated by γ-irradiation [22].…”

Section: Introductionmentioning

confidence: 87%

Charge Storage and Reliability Characteristics of Nonvolatile Memory Capacitors with HfO2/Al2O3-Based Charge Trapping Layers

et al. 2022

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Flash memories are the preferred choice for data storage in portable gadgets. The charge trapping nonvolatile flash memories are the main contender to replace standard floating gate technology. In this work, we investigate metal/blocking oxide/high-k charge trapping layer/tunnel oxide/Si (MOHOS) structures from the viewpoint of their application as memory cells in charge trapping flash memories. Two different stacks, HfO2/Al2O3 nanolaminates and Al-doped HfO2, are used as the charge trapping layer, and SiO2 (of different thickness) or Al2O3 is used as the tunneling oxide. The charge trapping and memory windows, and retention and endurance characteristics are studied to assess the charge storage ability of memory cells. The influence of post-deposition oxygen annealing on the memory characteristics is also studied. The results reveal that these characteristics are most strongly affected by post-deposition oxygen annealing and the type and thickness of tunneling oxide. The stacks before annealing and the 3.5 nm SiO2 tunneling oxide have favorable charge trapping and retention properties, but their endurance is compromised because of the high electric field vulnerability. Rapid thermal annealing (RTA) in O2 significantly increases the electron trapping (hence, the memory window) in the stacks; however, it deteriorates their retention properties, most likely due to the interfacial reaction between the tunneling oxide and the charge trapping layer. The O2 annealing also enhances the high electric field susceptibility of the stacks, which results in better endurance. The results strongly imply that the origin of electron and hole traps is different—the hole traps are most likely related to HfO2, while electron traps are related to Al2O3. These findings could serve as a useful guide for further optimization of MOHOS structures as memory cells in NVM.

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“…The degradation of the memory window during the repeated write/erase operations is most likely due to wear-out mechanisms such as the generation of new bulk shallow traps and charges and interface state generation at the Si interface [46]. We have also investigated the radiation hardness of HfO2/Al2O3 CTL [47]. For this aim, the as-deposited and annealed 5×(30:10) stacks were subjected to 60 Co γ -irradiation with two radiation doses (10 and 100 kGy).…”

Section: Composition Of Charge Trapping Layermentioning

confidence: 99%

“…For this aim, the as-deposited and annealed 5×(30:10) stacks were subjected to 60 Co γ -irradiation with two radiation doses (10 and 100 kGy). During irradiation, no bias was applied to the We have also investigated the radiation hardness of HfO 2 /Al 2 O 3 CTL [47]. For this aim, the as-deposited and annealed 5×(30:10) stacks were subjected to 60 Co γ -irradiation with two radiation doses (10 and 100 kGy).…”

Section: Composition Of Charge Trapping Layermentioning

confidence: 99%

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Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks

Spassov,

Paskaleva

2023

Nanomaterials

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The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells—e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.

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Radiation Tolerance and Charge Trapping Enhancement of ALD HfO2/Al2O3 Nanolaminated Dielectrics

Cited by 8 publications

References 55 publications

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device

Charge Storage and Reliability Characteristics of Nonvolatile Memory Capacitors with HfO2/Al2O3-Based Charge Trapping Layers

Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks

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