Massively parallel programming models used as hardware description languages: The OpenCL case

Owaida,; Bellas, Nikolaos; Antonopoulos, Christos D.; Daloukas,; Antoniadis, Charalampos

doi:10.1109/iccad.2011.6105349

Cited by 10 publications

(7 citation statements)

References 11 publications

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“…Owaida et al [19] describe an automatic methodology to synthesize OpenCL workgroups into hardware accelerators for FPGA targets. The internal core of the accelerators works in a streaming-like fashion on data that is prefetched by a request generator that can directly access system memory.…”

Section: Related Workmentioning

confidence: 99%

Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters

Conti¹,

Marongiu²,

Benini³

2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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Several many-core designs tackle scalability issues by leveraging tightly-coupled clusters as building blocks, where lowlatency, high-bandwidth interconnection between a small/medium number of cores and L1 memory achieves high performance/watt. Tight coupling of hardware accelerators into these multicore clusters constitutes a promising approach to further improve performance/area/watt. However, accelerators are often clocked at a lower frequency than processor clusters for energy efficiency reasons. In this paper, we propose a technique to integrate shared-memory accelerators within the tightly-coupled clusters of the STMicroelectronics STHORM architecture. Our methodology significantly relaxes timing constraints for tightly-coupled accelerators, while optimizing data bandwidth. In addition, our technique allows to operate the accelerator at an integer submultiple of the cluster frequency. Experimental results show that the proposed approach allows to recover up to 84% of the slow-down implied by reduced accelerator speed.

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Section: Related Workmentioning

confidence: 99%

Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters

Conti¹,

Marongiu²,

Benini³

2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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“…The FPGA Brook implementation uses 18,909 LEs, 63 9-bit multipliers, and 33 4-Kbit memory blocks. Another related paper [Owaida et al 2011] uses matrix multiplication as a benchmark, but uses floating point arithmetic, making it difficult to perform a meaningful comparison. Altera [2012b] reported 60X speedup over the Nios II processor when implementing the Mandelbrot application using manually tuned C2H code that was written in a way that allowed the hardware implementation to take advantage of data parallelism.…”

Section: Mandelbrot Setmentioning

confidence: 99%

“…Their results also show that the circuits generated by the Optimus compiler significantly outperform the embedded PowerPC processor, which is similar to our results relative to the Nios II soft processor. Other related projects include FCUDA [Papakonstantinou et al 2009], which compiles CUDA kernels to FPGA logic, and compilers mapping applications described in OpenCL to FPGA logic [Altera 2012e;Lin et al 2010;Owaida et al 2011]. …”

Section: Related Workmentioning

confidence: 99%

Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs

Plavec

Vranesic

Brown

2013

ACM Trans. Reconfigurable Technol. Syst.

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This article describes the design and implementation of a novel compilation flow that implements circuits in FPGAs from a streaming programming language. The streaming language supported is called FPGA Brook and is based on the existing Brook language. It allows system designers to express applications in a way that exposes parallelism, which can be exploited through hardware implementation. FPGA Brook supports replication, allowing parts of an application to be implemented as multiple hardware units operating in parallel. Hardware units are interconnected through FIFO buffers which use the small memory modules available in FPGAs. The FPGA Brook automated design flow uses a source-to-source compiler, developed as a part of this work, and combines it with a commercial behavioral synthesis tool to generate the hardware implementation. A suite of benchmark applications was developed in FPGA Brook and implemented using our design flow. Experimental results indicate that performance of many applications scales well with replication. Our benchmark applications also achieve significantly better results than corresponding implementations using a commercial behavioral synthesis tool. We conclude that using an automated design flow for implementation of streaming applications in FPGAs is a promising methodology.

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“…In contrast to this platform, we propose a workgroup synthesis techniques to efficiently map OpenCL applications that process large amount of data on a very resourcerestricted FPGA in the Xilinx Zynq SoC. Owaida et al [3] propose a source-to-source converter to generate a C code from the OpenCL kernel code. They utilise compiler techniques such as prediction, code slicing and modulo scheduling to convert the C code into an HDL code to be synthesised by synthesis tools considering a hardware architecture.…”

Section: Previous Workmentioning

confidence: 99%

“…This critical innovation could make FPGA devices accessible to software programmers as an additional computing resource without changes to the algorithm source code. A few commercial and research OpenCL frameworks have been proposed by industry and researchers [3][4][5][6][7]. The commercially available OpenCL frameworks recommend that designers should structure their OpenCL kernel as a single workitem kernel (instead of NDRange kernels) if it is possible to improve performance [8].…”

Section: Introductionmentioning

confidence: 99%

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices

Hosseinabady

Nunez-Yanez

2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-This paper presents a workgroup synthesis mechanism to compile an OpenCL kernel to FPGA-based accelerators embedded in a multi-core CPU system-on-a-chip (SoC). The OpenCL kernels considered in this paper exhibit regular data access patterns. Coping with the limited amount of internal memory in embedded FPGAs, the workgroup synthesis utilises a novel data access pattern formulation to describe the parallelism already provided by the OpenCL kernels. To provide an OpenCL framework prototype to validate the proposed technique, a source-to-source compiler that transforms the OpenCL kernel into C/C++ code is developed. Then vendor-specific high-level synthesis tools are used to convert the C/C++ code into the FPGA bitstream. Results based on popular real applications show up to 89.8% improvement in the execution time compared to the commercial FPGA OpenCL implementations.

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Massively parallel programming models used as hardware description languages: The OpenCL case

Cited by 10 publications

References 11 publications

Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters

Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters

Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs

Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices

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