Managing the FPGA memory wall: Custom computing or vector processing?

Naylor, Matthew; Fox, Paul J.; Markettos, A. Theodore; Moore, Simon W.

doi:10.1109/fpl.2013.6645538

Cited by 18 publications

(15 citation statements)

References 9 publications

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“…Further work has been done to customize vector processors for FPGAs, with the most recent being the VectorBlox MXP [9] which has the ability to dispatch multi-operand custom instructions to the external FPGA fabric. Additional work on applications and programmability has been done at University of Cambridge [8] where a neural network simulation was implemented and a C++ library developed to encapsulate vectors as objects.…”

Section: Fpga-based Soft Vector Processorsmentioning

confidence: 99%

Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors

Severance

Edwards

Lemieux

2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Soft vector processors can accelerate data parallel algorithms on FPGAs while retaining software programmability. To handle divergent control flow, vector processors typically use mask registers and predicated instructions. These work by executing all branches and finally selecting the correct one. Our work improves FPGA based vector processors by adding wavefront skipping, where wavefronts that are completely masked off are skipped. This accelerates conditional algorithms, particularly useful where elements terminate early if simple tests fail but require extensive processing in the worst case. The difference in logic speed and RAM area for FPGA based circuits versus ASICs led us to a different implementation than used in fixed vector processors, storing wavefront offsets in on-chip BRAM rather than computing wavefronts skipped dynamically. Additionally, we allow for partitioning the wavefronts so that partial wavefronts can skip independently of one another. We show that <5% extra area can give up to 3.2× better performance on conditional algorithms. Partial wavefront skipping may not be generally useful enough to be added to a fixed vector processor; it provides up to 65% more performance for up to 27% more area. In an FGPA, however, the designer can use it to make application specific tradeoffs between area and performance.

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Section: Fpga-based Soft Vector Processorsmentioning

confidence: 99%

Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors

Severance

Edwards

Lemieux

2015

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…At this scale, around 1 nm, the properties of the semi-conductor material in the active region of a transistor are compromised by quantum effects like quantum tunneling. In addition, there are also other limitations, such as the energy wall [69,70] and memory wall [71], which denote the high power density and low memory bandwidth [72,73]. There are also economic limitations, since the cost of designing a chip and the cost of building a fabrication facility are growing alarmingly [74].…”

Section: Neuromorphic Chipsmentioning

confidence: 99%

Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

Pastur-Romay

Cedrón

Pazos

et al. 2016

IJMS

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Over the past decade, Deep Artificial Neural Networks (DNNs) have become the state-of-the-art algorithms in Machine Learning (ML), speech recognition, computer vision, natural language processing and many other tasks. This was made possible by the advancement in Big Data, Deep Learning (DL) and drastically increased chip processing abilities, especially general-purpose graphical processing units (GPGPUs). All this has created a growing interest in making the most of the potential offered by DNNs in almost every field. An overview of the main architectures of DNNs, and their usefulness in Pharmacology and Bioinformatics are presented in this work. The featured applications are: drug design, virtual screening (VS), Quantitative Structure–Activity Relationship (QSAR) research, protein structure prediction and genomics (and other omics) data mining. The future need of neuromorphic hardware for DNNs is also discussed, and the two most advanced chips are reviewed: IBM TrueNorth and SpiNNaker. In addition, this review points out the importance of considering not only neurons, as DNNs and neuromorphic chips should also include glial cells, given the proven importance of astrocytes, a type of glial cell which contributes to information processing in the brain. The Deep Artificial Neuron–Astrocyte Networks (DANAN) could overcome the difficulties in architecture design, learning process and scalability of the current ML methods.

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“…The whole system was implemented in Bluespec SystemVerilog (BSV), which was interfaced to our interconnect via simple FIFO bridges. We have also implemented a vector processing system for the same neural simulation task [19]. Altera NIOS II processors facilitate control the execution of our BlueVec vector processors and communicate using our interconnect via bridges that present a memory-mapped interface to our interconnect.…”

Section: Example Applicationsmentioning

confidence: 99%

Reliably prototyping large SoCs using FPGA clusters

Fox

Markettos

Moore

2014

2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Abstract-Prototyping large SoCs (Systems on Chip) using multiple FPGAs introduces a risk of errors on inter-FPGA links. This raises the question of how we can prove the correctness of a SoC prototyped using multiple FPGAs. We propose using high-speed serial interconnect between FPGAs, with a transparent error detection and correction protocol working on a link-by-link basis. Our inter-FPGA interconnect has an interface that resembles that of a network-on-chip, providing a consistent interface to a prototype SoC and masking the difference between on-chip and off-chip interconnect. Lowlatency communication and low area usage are favoured at the expense of a little bandwidth inefficiency, a trade-off we believe is appropriate given the high bandwidth of inter-FPGA links.

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Managing the FPGA memory wall: Custom computing or vector processing?

Cited by 18 publications

References 9 publications

Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors

Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors

Deep Artificial Neural Networks and Neuromorphic Chips for Big Data Analysis: Pharmaceutical and Bioinformatics Applications

Reliably prototyping large SoCs using FPGA clusters

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