Maintaining the benefits of CMOS scaling when scaling bogs down

Nowak, E.

doi:10.1147/rd.462.0169

Cited by 187 publications

(78 citation statements)

References 23 publications

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“…For reference, advanced FETs have respective V T and S parameters of 100-200 mV, and ∼70-90 mV/decade [33]. At V ds = 1.43 V, P g = 0.11 µW yields I ds ≈ 0.35 µA, and a LET dynamic power consumption of ∼0.5 µW, which is comparable to advanced FETs [34]. A LET's off-state energy consumption can be very low.…”

Section: Output and Transfer Characteristicmentioning

confidence: 99%

“…A LET's off-state energy consumption can be very low. For instance, the dark current is ∼1 pA at V ds = 1.43 V with a corresponding off power consumption of ∼1.5 pW, which is lower than a FET of similar length [34]. Switching energy, or the amount of energy needed to go from off to on states, is a frequently quoted metric.…”

Section: Output and Transfer Characteristicmentioning

confidence: 99%

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Light-Effect Transistor (LET) with Multiple Independent Gating Controls for Optical Logic Gates and Optical Amplification

et al. 2016

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Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g., field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore's law to the quantum region without requiring a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to ∼1.0 × 10 6 with a source-drain voltage of ∼1.43 V, gate-power of ∼260 nW, and a subthreshold swing of ∼0.3 nW/decade (excluding losses). Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

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Section: Output and Transfer Characteristicmentioning

confidence: 99%

Section: Output and Transfer Characteristicmentioning

confidence: 99%

Light-Effect Transistor (LET) with Multiple Independent Gating Controls for Optical Logic Gates and Optical Amplification

et al. 2016

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“…A one-time voltage reduction can improve power efficiency for parallelizable applications without system performance degradation, but power densities may increase in future technologies due to limitations in further voltage scaling. Adapted from Nowak [11]. modern technologies is significantly higher than originally suggested by scaling theory [11].…”

Section: A Mosfet Scaling Theorymentioning

confidence: 99%

“…Due to leakage and variability constraints, voltage levels have deviated significantly from constant field scaling theory [2]. Adapted from Nowak [11]. Fig.…”

Section: A Mosfet Scaling Theorymentioning

confidence: 99%

Practical Strategies for Power-Efficient Computing Technologies

et al. 2010

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| After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $ 8Â improvement in power efficiency can be attained without system performance loss in parallelizable applicationsVthose in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

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“…According to [4], [10], [11], we can use a projected value of leakage power density around (3W/cm 2 ) for a 70nm technology node. Although, as the area of a module increases, random variations tend to decrease the ratio between standard deviation and the average power, we currently lack of information on the specific behavior.…”

Section: Background On Variability Aware Delay and Energy Models mentioning

confidence: 99%

Variability-aware robust design space exploration of chip multiprocessor architectures

Palermo¹,

Silvano²,

Zaccaria³

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufacturing process variations. First, we introduce response surface modeling techniques to enable an efficient evaluation of the statistical measures of execution time and energy consumption for each system configuration. We then introduce a robust design space exploration framework to afford the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints. We finally provide a comparison of our design space exploration technique with conventional approaches. 1 I. INTRODUCTION Process variation is dramatically becoming one of the most important challenges related to power and performance optimization for sub-90 nm CMOS technologies. Parametric yield, i.e., the percentage of dies that meet power and performance constraints, has become as important as power and performance optimization itself.Manufacturing process variability is mainly due to inter-die and intra-die variations. Inter and intra-die variations affect low level process parameters such as the channel gate length, the thickness of the oxide and the threshold voltage, which, in turn, affect the critical path delay and static and dynamic power consumption. Inter-die fluctuations affect uniformly every element on a die and consist of lot-to-lot and wafer-towafer variations such as processing temperatures, equipment properties, wafer polishing, wafer placement and the resist thickness. Conversely, intra-die parameter fluctuations consist of both random and systematic components and generate nonuniform electrical characteristics across the chip [1].In this scenario, we address the problem of variabilityaware design at system-level for chip multi-processors (CMP). More precisely, we tackle the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints.The main contribution of this paper is twofold:• We introduce a design space exploration (DSE) framework which is robust with respect to manufacturing process variations. The main goal is the optimization of the dispersion of the target system metrics and the maximization of the yield of the system with respect to the application-level constraints.• The exploration process is supported by response surface modeling (RSM) techniques for improving the overall estimation time to obtain the system-level metrics associated to each system configuration. The DSE framework is based on a set of state-of-the-art accurate performance, area and energy models of a CMP

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Maintaining the benefits of CMOS scaling when scaling bogs down

Cited by 187 publications

References 23 publications

Light-Effect Transistor (LET) with Multiple Independent Gating Controls for Optical Logic Gates and Optical Amplification

Light-Effect Transistor (LET) with Multiple Independent Gating Controls for Optical Logic Gates and Optical Amplification

Practical Strategies for Power-Efficient Computing Technologies

Variability-aware robust design space exploration of chip multiprocessor architectures

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