Macro-Model for Post-Breakdown 90NM and 130NM Transistors and its Applications in Predicting Chip-Level Function Failure after ESD-CDM Events

Gate oxide reliability characterization in the 100ps regime with ultra-fast transmission line pulsing system

“…As can be seen, if the leakage current exceeds 10µA, the gate oxide is already completely broken-down, and the leakage current will quickly degrade to 300µA. It has been previously reported that some cells can continue to function correctly as long as the gate leakage resistance is high enough [2,10]. Thus, this stable gate leakage resistance after SBD will enable designers to relax oxide reliability requirements.…”

“…It has been recently reported that inductive coupling during ESD-CDM (Charged Device Model) events can cause short transient pulses (~100ps) with high voltages (>17V) to appear on the gates of transistors in the core of an integrated circuit [1,2]. These high voltages can cause logic function failure in some, but not all, cases.…”