ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies

Cao, Shuqing; Chun, Jung-Hoon; Beebe, S.; Dutton, R.W.

doi:10.1109/tcsi.2010.2071590

Cited by 25 publications

(6 citation statements)

References 40 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1. The ESD protections used in this work are based on diode-triggered silicon-controller rectifiers [31], [32] and are designed to be compliant with the 2 kV human-body model and 500 V machine model. They were reused from previous projects since they have already been qualified for sustaining high radiation doses.…”

Section: A Output Load Modelingmentioning

confidence: 99%

“…The electrical measurements are performed by exciting the device under test (DUT) with a 2 32 -1 combinations-long pseudo random binary sequence (PRBS-31) generated by a Kintex Ultrascale FPGA and using a 23 GHz 100 GS/s Tektronix oscilloscope to acquire the output signals. The oscilloscope disturbs the signal measurement by introducing a 50 loading impedance shunt to ground.…”

Section: A Electrical Measurementsmentioning

confidence: 99%

See 1 more Smart Citation

Design and Characterization of 10 Gb/s and 1 Grad TID-Tolerant Optical Modulator Driver

Ciarpi

Cammarata

Monda

et al. 2022

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

This paper presents the design and the experimental characterization of a 10 Gb/s electronic driver for silicon Mach-Zehnder modulators (MZMs). This driver is able to operate in harsh environments characterized by radiation levels up to 1 Grad(SiO 2 ) total ionizing dose (TID). To compensate for the detrimental effects that radiation produces on the target 65 nm bulk silicon technology both device-and circuit-level radiation hardened by design (RHBD) techniques are developed and implemented. Extreme TID levels are faced using longchannel transistors with enclosed layout, avoiding the use of p-MOSFETs, and implementing a differential self-biased cascode architecture with common-mode feedback. Band-widening techniques, e.g., inductive peaking, cross-coupled capacitors, and buffer chaining, have been used to improve the driver's frequency response and reach the targeted data rate. Electrical measurements show 10 Gb/s waveforms with an eye diagram amplitude suitable for MZM driving. Electro-optical measurements performed connecting the electronic driver to a silicon photonic MZM confirm the achievement of a 10 Gb/s systemlevel operability. The radiation hardness of the driver is verified by exposing the integrated circuit to X-rays. The measurements confirm the ability of the driver to work up to 1 Grad with an eye amplitude reduction of only 10% and a 7% increment in the rise and fall times, validating the effectiveness of the implemented RHBD techniques.

show abstract

Section: A Output Load Modelingmentioning

confidence: 99%

Section: A Electrical Measurementsmentioning

confidence: 99%

Design and Characterization of 10 Gb/s and 1 Grad TID-Tolerant Optical Modulator Driver

Ciarpi

Cammarata

Monda

et al. 2022

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…The scaling of semiconductor technology unfavorably impacts on-chip ESD protection performance by decreasing I/O MOSFET oxide breakdown voltage (V break ) and parasitic bipolar junction trigger level (LBJT V t1 ) [1][2][3][4]. The reduction of metal interconnect thickness increases its resistivity, causing high pad voltage during ESD.…”

Section: Technology Trendsmentioning

confidence: 99%

Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

Cao

Chun

Salman

et al. 2011

Microelectronics Reliability

Self Cite

View full text Add to dashboard Cite

“…ESD protection in high-speed ICs becomes more challenging than others because it requests low parasitic capacitance, low leakage current and almost zero series resistance [8,9,10]. To address this, dual-diode based ESD protection circuits, often named "rail-based" ESD protection circuits [11], are widely implemented for radio-frequency (RF), digital and high-speed interface ICs [12,13,14,15,16,17,18,19,20,21]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits

Lai

Wang

et al. 2019

IEICE Electron. Express

View full text Add to dashboard Cite

In this paper, ESD triggering mechanism of the parasitic PNP bipolar transistor in rail-based ESD protection circuits was investigated. The device simulation results show that the triggering voltage of the parasitic PNP varies with the geometry of the base region (e.g., the spacing between P+ and N-well). Furthermore, the test structures of parasitic PNP devices with different width of collector and base region were fabricated using the 65 nm low-k logic/Mixed-Mode CMOS process and characterized with the transmission line pulse (TLP) system. Both simulation and experimental results demonstrated that the triggering voltage of parasitic PNP structures has strong dependence on the base region and the simulation results also show that the triggering voltage is significantly affected by the spacing between P-well and N-well.

show abstract

ESD Design Strategies for High-Speed Digital and RF Circuits in Deeply Scaled Silicon Technologies

Cited by 25 publications

References 40 publications

Design and Characterization of 10 Gb/s and 1 Grad TID-Tolerant Optical Modulator Driver

Design and Characterization of 10 Gb/s and 1 Grad TID-Tolerant Optical Modulator Driver

Gate-controlled field-effect diodes and silicon-controlled rectifier for charged-device model ESD protection in advanced SOI technology

Investigation of parasitic bipolar transistor in rail-based electrostatic discharge (ESD) protection circuits

Contact Info

Product

Resources

About