Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome

Abstract

The genetic algorithm has been applied to the VLSI module placement problem. This algorithm is an iterative, evolutional approach. A placement configuration is represented by a set of primitive features such as location and orientation, and the features are arranged in the form of a two-dimensional bitmap chromosome. The representation is flexible, and can handle arbitrarily shaped cells, and pads, and is applicable to the placement of macro cells, and gate arrays. Three new versions of genetic operators, namely, crossover, inversion and mutation, are used to explore the solution space. Crossover creates new configurations by combining attributes from a pair of existing configurations. This feature passing scheme constitutes the primary difference between our genetic approach and the other traditional searching techniques. Inversion enables more uniform inheritance of features from one generation to the next, and mutation prevents the algorithm from getting trapped at local optima. We have pointed out that the bitmap representation enables the algorithm to divide the entire solution space into a set of feature-equivalent classes, or schemata where each class contains a set of solutions with common physical attributes. We show that the genetic algorithm adaptively biases the search based on the past observed fitness of the schemata. We also demonstrated the power of the genetic algorithm experimentally for macro cell placement, and obtained satisfactory results.

Aladin: A Layout Synthesys Tool for Analog Integrated Circuits

“…Although theoretically this scheme has the advantage to cover every possible topology, the great complexity of multi-dimensional configuration space in the placement problem practically prevents the search. Consequently, the layout result in [31] is rather sparse. Even worse, according to our experimental study, the symmetry constraints, which are critical to the analog layout designs, increase the complexity of configuration space.…”

“…According to it, the placement can be categorized into two portions: absolute placement and relative placement. Flat placement, also called Jepsen-Gelatt style used in [11,13,31], is a kind of absolute placement, where a placement is represented by specifying the absolute coordinates of modules. Although theoretically this scheme has the advantage to cover every possible topology, the great complexity of multi-dimensional configuration space in the placement problem practically prevents the search.…”

A enhanced algorithm for floorplan design using evolutionary technique

“…It includes the assignment of circuit elements to locations on the chip. The objective of placement is to minimize the layout area of the chip [3][4][5] .…”

An Investigation of PWB Layout by Genetic Algorithms to Maximize Fatigue Life

“…These electronic component placement problems have been considered by a number of researchers. Most of the papers ( [Cohoon and Paris, 1986], [Shahookar and Mazumder, 1990], [Chan, Heming et al, 1991]) examine placement of modules on a VLSI chip to minimize chip area and interconnect lengths. [Jin and Chan, 1992] extended the same performance metrics to discrete analog (through hole) components.…”