&lt;title&gt;New programmable video signal processor for motion estimation and motion compensation&lt;/title&gt;

Gong, Danian; He, Yun

doi:10.1117/12.411875

Cited by 4 publications

(2 citation statements)

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“…To make the implementation achieve sufficient programmability, the key algorithms in video compression are studied and abstracted. Let us take ME as an instance: variant block match algorithms can be expressed by five parameters [3]. Based on these studies, the flexible and high efficient architecture of each module is designed.…”

Section: Arceiteciztres Of Pvspmentioning

confidence: 99%

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A single-chip real-time programmable video signal processor

Gong

2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)

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In this paper, we describe a cost-efficient programmable video signal processor (PVSP) to implement various video encoding and decoding schemes. Hierarchical (two levels) programmable control architecture, flexible memory address mapping strategies and a p r o g m a b l e VLCNLD module are applied in order to achieve sufficient programmability. Thus, PVSP can support various video compression algorithms and standards, such as MPEG-1, MPEG-2 H.263, and MPEG-4. Meanwhile, to improve the throughput of this codec system, some paralleling approaches are exploited on different levels, which include pipeline, tree adder, and SIMD (single instruction stream, multiple data streams). PVSP is estimated to have approximately 320k gates and it can accomplish MPEG-2 MP@ML encoding in real-time at the frequency of 133MHz.

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Section: Arceiteciztres Of Pvspmentioning

confidence: 99%

“…The rest units will be discussed in detail in the following of this section. TA sub-module is a regular, iterative and low-delay tree adder, which has not any pipeline stages and is the key computation component to implementation block match algorithm [3]. PMA is an SIMD module with eight identical multiply accumulators (MA).…”

Section: Arceiteciztres Of Pvspmentioning

confidence: 99%