A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms

Vanne, Jarno; Aho, Eero; Hämäläinen, Timo D.; Kuusilinna, Kimmo

doi:10.1109/tcsvt.2008.918273

Cited by 16 publications

(12 citation statements)

References 12 publications

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“…We use the estimating method similar as that in paper [2]: The area cost of λ-input basic gates is assumed to be λ cost-units (CUs), with the exception that XOR/XNOR has 2λ CUs. For all the 2-input gates the delay is assumed to be 1 τ .…”

Section: Hardware Complexity Of Pm Controllersmentioning

confidence: 99%

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A novel parallel memory organization supporting multiple access types with matched memory modules

Liu

Chen

et al. 2012

IEICE Electron. Express

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This paper introduces a Bilinear Skewed Parallel Memory (BilisPM), which can support multiple conflict-free access types and the circular addressing in X-Y directions of the 2D space. BilisPM features matched Memory Modules (MMs) and can effectively save the on-chip area. We introduce the formal specifications of BilisPM and give its hardware implementation. Experimental results show that BilisPM can reduce the chip area by 22.7% on average (38.1% at most), and its controller consumes smaller chip area at reasonable critical path delay, as compared with the traditional schemes with unmatched MMs.

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Section: Hardware Complexity Of Pm Controllersmentioning

confidence: 99%

“…Conventional simple PM schemes [1,2,3] cannot simultaneously support enough access types without conflicts due to their matched MMs. Here "matched" means that if the SIMD data path width is M×N, the number of needed MMs will be also M×N.…”

Section: Introductionmentioning

confidence: 99%

A novel parallel memory organization supporting multiple access types with matched memory modules

Liu

Chen

et al. 2012

IEICE Electron. Express

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“…There were mainly three module assignment functions of the 2D Memory, proposed by Kuzmanov [4], Vanne [5], and Tian [6]. Although our LP2D is based on Vanne's 2D memory, it can also be applied to the schemes proposed by Kuzmanov [4] and Tian [6].…”

Section: Motivationmentioning

confidence: 99%

“…When mapped on a vector DSP with the 1D memory, these applications will suffer the performance degradation resulting from irregular data accesses. The 2D memory [3,4,5,6], that uses the 'X' and 'Y' coordinates to denote the memory space, can keep the 2D relation among pixels steady and support conflict-free block accesses, thus increasing the data reutilization and improve the performance of sliding-window applications.…”

mentioning

confidence: 99%

LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs

Liu

Chen

Ning

et al. 2011

IEICE Electron. Express

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Abstract:The power consumption of the 2D memory restricts its usage in vector DSPs for sliding-window applications with irregular memory accesses. This paper introduces a novel Low-Power 2D memory (LP2D), which can effectively reduce the power consumption to the traditional 2D memory without sacrificing its performance. By the theory analysis, we design an adjacent address checker which can generate the bank control mask to turn off some power-sensitive circuits of the 2D memory. Experimental results show that the LP2D can reduce the power consumption by 31.7%∼62.9% with less than 1.3% additional hardware cost, as compared with the traditional 2D memory schemes.

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“…The configurable and parallel nature of FPGAs makes them an attractive choice for accelerating various multimedia tasks such as ME [3,6]. In order to implement an FBM algorithm on an FPGA, two types of modules are required: (i) Processing Element (PE) to compute SAD, and (ii) Memory subsystem to store and supply the pixel data of the video frames.…”

Section: Introductionmentioning

confidence: 99%

Memory architecture template for Fast Block Matching algorithms on FPGAs

Chandrakar

Clements

Sudarsanam

et al. 2010

2010 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum (IPDPSW)

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Fast Block Matching (FBM) algorithms for video compression are well suited for acceleration using parallel data-path architectures on Field Programmable Gate Arrays (FPGAs). However, designing an efficient on-chip memory subsystem to provide the required throughput to this parallel data-path architecture is a complex problem. This thesis presents a memory architecture template that can be parameterized for a given FBM algorithm, number of parallel Processing Elements (PEs), and block size. The template can be parameterized with well known exploration techniques to design efficient on-chip memory subsystems. The memory subsystems are derived for two existing FBM algorithms and are implemented on a Xilinx Virtex 4 family of FPGAs. Results show that the derived memory subsystem in the best case supports up to 27 more parallel PEs than the three existing subsystems and processes integer pixels in a 1080p video sequence up to a rate of 73 frames per second. The speculative execution of an FBM algorithm for the same number of PEs increases the number of frames processed per second by 49%.

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A Parallel Memory System for Variable Block-Size Motion Estimation Algorithms

Cited by 16 publications

References 12 publications

A novel parallel memory organization supporting multiple access types with matched memory modules

A novel parallel memory organization supporting multiple access types with matched memory modules

LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs

Memory architecture template for Fast Block Matching algorithms on FPGAs

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