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Multi-channel memories can be organized in a variety of ways to optimize for different kinds of memory loads. However, their efficient configuration and management in mobile environment is not obvious. In this paper, a SystemC model of a multi-channel memory is constructed out of low power double data rate SDRAMs. The model is simulated with sketchy load in order to gain understanding how memory access size and number of channels affect access times and power figures. The simulations confirm that applications with large data accesses benefit from the multi-channel memories. When used properly, multi-channel memories provide the capability for high throughput but do not introduce excessive overhead compared to single-channel memories in terms of energy consumption. The experiments also reveal that relatively small accesses can be extremely expensive if the memory is not properly configured. In future systems, novel policies, advanced control mechanisms, and reorganization of traditional memory management are needed to keep the power consumption manageable.

Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory architecture allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the data patterns have equal amount of accessed data elements as the number of memory modules. The complexity is evaluated with resource counts.

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