Parallel Memory Architecture for Arbitrary Stride Accesses

Aho, Eero; Vanne, Jarno; Hämäläinen, Timo D.

doi:10.1109/ddecs.2006.1649572

Cited by 8 publications

(4 citation statements)

References 11 publications

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“…This theorem follows Theorem 1 from[1] but in our case it is generalized since it considers the group length together with the stride.…”

mentioning

confidence: 81%

“…The initial problem partitioning is done based on the stride oddness. Theorem 2 suggests that odd strides can be accessed conflict-free using a basic skewing scheme [1], [6]. Furthermore, all odd and even strides are divided into six subgroups.…”

Section: Proposed Memory Access Schemementioning

confidence: 99%

“…Such caches, however, fail to provide any performance benefits to vector machines or to applications with spatial locality such as multidimensional (e.g., 2D) matrix computations, multimedia, etc. In SIMD processors, this memory performance bottleneck is often prevented by interleaved memory systems, also referred to as space-multiplexed memories [1]. In these memory systems, parallel memory modules are organized to access application specific data patterns and to feed the processing units with data in a concurrent manner.…”

Section: Introductionmentioning

confidence: 99%

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Memory organization with multi-pattern parallel accesses

Vitkovski

Kuzmanov

Gaydadjiev

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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We propose an interleaved memory organization supporting multi-pattern parallel accesses in twodimensional (2D) addressing space. Our proposal targets computing systems with high memory bandwidth demands such as vector processors, multimedia accelerators, etc. We substantially extend prior research on interleaved memory organizations introducing 2D-strided accesses along with additional parameters, which define a large variety of 2D data patterns. The proposed scheme guarantees minimum memory latency and efficient bandwidth utilization for arbitrary configuration parameters of the data pattern. We provide mathematical descriptions and proofs of correctness for the proposed addressing schemes. The design complexity and the critical paths are evaluated using technology independent resource counts and confirm the scalability of the proposal. Hardware synthesis results for 90nm CMOS technology suggest that throughputs in the range between 44 and 1182 Gbit/s can be obtained at the cost of 26-212 Kgates for configurations of 2x2 32-bit up to 8x8 64-bit memory modules.Index Terms-Conflict-free access, high bandwidth, multi-pattern access, parallel memories.

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“…This theorem follows Theorem 1 from[1] but in our case it is generalized since it considers the group length together with the stride.…”

mentioning

confidence: 81%

Section: Proposed Memory Access Schemementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Memory organization with multi-pattern parallel accesses

Vitkovski

Kuzmanov

Gaydadjiev

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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“…A new stride with a possible new scheme is demanded only when new input image data is written to parallel memories. This paper is based on previous research results shown in [18] and [19]. Section 2 presents the problems with contemporary data memories tailored for multimedia processing and gives the motivation for parallel stride access.…”

Section: Introductionmentioning

confidence: 99%

Configurable Data Memory for Multimedia Processing

Aho

Vanne

Hämäläinen

2007

J Sign Process Syst Sign Image

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In modern multimedia applications, memory bottleneck can be alleviated with special stride data accesses. Data elements in stride access can be retrieved in parallel with parallel memories, in which the idea is to increase memory bandwidth with several memory modules working in parallel and feed the processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the accessed data element count equals to the number of memory modules. Timing and area estimates are given for Altera Stratix FPGA and 0.18 micrometer CMOS process with memory module count from 2 to 32. The FPGA results show 129 MHz clock frequency for a system with 16 memory modules when read and write latencies are 3 and 2 clock cycles, respectively. The complexity of the proposed system is shown to be a trade-off between application specific and highly configurable parallel memory system.

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