Byte and Modulo Addressable Parallel Memory Architecture for Video Coding

Tanskanen, Jarno M. A.; Sihvo, T.; Niittylahti, J.

doi:10.1109/tcsvt.2004.835148

Cited by 19 publications

(14 citation statements)

References 11 publications

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“…In such systems, the skewing scheme is implicitly embedded in the hardware. Some examples are the systems by Aho, Vanne, Tanskanen [58], and Kuzmanov.…”

Section: Discussionmentioning

confidence: 99%

“…A byte and modulo addressable parallel memory architecture for video coding is proposed by Tanskanen et al [58]. Byte addressing means that a row access format can arbitrarily be located conflict free in the scanning field, i.e.…”

Section: Evaluated Parallel Memory Implementationsmentioning

confidence: 99%

“…The excluded functionality concerns mainly pipeline stalling. In Tanskanen_s memories, the given transistor counts in [58] and [59] are converted into gate counts by supposing four transistors per a single 2-input NAND gate. The results shown in [6] contain only the most complex parts of Table 8.…”

Section: Complexity Of the Implementationsmentioning

confidence: 99%

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Configurable Data Memory for Multimedia Processing

Aho

Vanne

Hämäläinen

2007

J Sign Process Syst Sign Image

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In modern multimedia applications, memory bottleneck can be alleviated with special stride data accesses. Data elements in stride access can be retrieved in parallel with parallel memories, in which the idea is to increase memory bandwidth with several memory modules working in parallel and feed the processor with only necessary data. Arbitrary stride access capability with interleaved memories is described in previous research where the skewing scheme is changed at run time according to the currently used stride. This paper presents the improved schemes which are adapted to parallel memories. The proposed novel parallel memory implementation allows conflict free accesses with all the constant strides which has not been possible in prior application specific parallel memories. Moreover, the possible access locations are unrestricted and the accessed data element count equals to the number of memory modules. Timing and area estimates are given for Altera Stratix FPGA and 0.18 micrometer CMOS process with memory module count from 2 to 32. The FPGA results show 129 MHz clock frequency for a system with 16 memory modules when read and write latencies are 3 and 2 clock cycles, respectively. The complexity of the proposed system is shown to be a trade-off between application specific and highly configurable parallel memory system.

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“…In such systems, the skewing scheme is implicitly embedded in the hardware. Some examples are the systems by Aho, Vanne, Tanskanen [58], and Kuzmanov.…”

Section: Discussionmentioning

confidence: 99%

Section: Evaluated Parallel Memory Implementationsmentioning

confidence: 99%

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Configurable Data Memory for Multimedia Processing

Aho

Vanne

Hämäläinen

2007

J Sign Process Syst Sign Image

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“…So it provides successive access for 4-point transform and even/odd access for 8-point transform to satisfy the requirements of cosine transforms [10]. The initial position (x,y) of successive access mode must verify the limitation shown in eq.…”

Section: Figure 5 Memory Mapping Of Blocksmentioning

confidence: 99%

“…The proposed parallel memory architecture contains three main building blocks, 4 half-word addressable memory modules, 4 way address calculation circuits and a crossbar network, as the same with popular architectures [10]. We employ the standard interleaved scheme to implement the above mapping of coefficients among the memory modules.…”

Section: Figure 6 Address Calculation Circuitsmentioning

confidence: 99%

An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding

Jian-ying

Qin

et al. 2007

2007 IEEE International Conf. On Application-Specific Systems, Architectures and Processors (ASAP)

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This paper proposes an efficient SIMD architecture with parallel memory for 2D cosine transforms of multiple video standards. A novel parallel memory scheme is employed to provide conflict-free parallel access in both horizontal and vertical directions with the successive or even/odd mode, as well as to eliminate data permutation and matrix transposition. Furthermore, application specific instructions are presented to accelerate the transform kernels, such as butterfly and rotate operations with scaling, rounding and clipping. The simulation results show that proposed architecture achieves significant performance improvement with low hardware cost of 3.2K equivalent gate count for parallel memory subsystem (not including SRAMs) and 19.8K for arithmetic units@250MHz in 0.18 µ m process.

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