LSI Surface Leveling by RF Sputter Etching

Homma, Yoshio; Harada, S.; Kaji, T.

doi:10.1149/1.2129322

Cited by 23 publications

(7 citation statements)

References 4 publications

(6 reference statements)

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“…Here, we describe the development of a robust and repeatable method for selectively modifying via etch-back technology the surface on a silica substrate with a microwell array. Etch-back is a traditional planarization technique used in semiconductor processes such as the leveling of large-scale integrated circuit surfaces and the dual damascene approach for integrated circuits, [26][27][28] its application can allow the separation between the microwell fabrication and surface modification processes. Thus, the site-selective hydrophilization and hydrophobization can perform to concise method.…”

Section: Introductionmentioning

confidence: 99%

A surface modification process for silica microreactor array chips to seal aqueous solutions

Sato¹,

Ueno²,

Ichikı³

2020

Jpn. J. Appl. Phys.

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In this study, we developed a surface modification process for silica microreactor array chips to enable a rapid and easy-to-use dispensation of aqueous solutions into their microwells. The etch-back method was adopted to perform the site-selective surface modification of a silica substrate with microwells (1 × 10 6 wells cm −2 , 50 fL/well); this technique maintains the hydrophilicity of the microwell inner walls and simultaneously introduces hydrophobicity onto the surface outside the microwells. The effectiveness of the modification was experimentally assessed by the successful isolation of an aqueous solution in the individual microreactors. This technique could be applied for the fabrication of microreactor array chips used in those fields requiring high-speed multiplex analysis of biomolecules, such as drug discovery and medical diagnosis.

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Section: Introductionmentioning

confidence: 99%

A surface modification process for silica microreactor array chips to seal aqueous solutions

Sato¹,

Ueno²,

Ichikı³

2020

Jpn. J. Appl. Phys.

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“…The yield and reliability of the devices produced often depend on the degree of smoothness of the polymer film. Finally, polymer films are becoming increasingly important as sac-rificial layers for etch-back processes (14)(15)(16)(17)(18)(19)(20)(21) in which polymer is spin coated on some topographically rough substrate that may be an insulator such as phosphosilicate glass or a conductor such as tungsten. The effect of the polymer coating is again to smooth the substrate.…”

mentioning

confidence: 99%

Mechanism for the Local Planarization of Microscopically Rough Surfaces by Drying Thin Films of Spin‐Coated Polymer/Solvent Solutions

Bornside

1990

J. Electrochem. Soc.

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When thin films of polymer/solvent solutions are spin coated onto microscopically rough substrates, the dry film profile tends to smooth or planarize those features of the substrate that have lateral dimensions on the order of micrometers and less. A mathematical model is used to explain the physical mechanisms that are responsible for this local planarization. The governing equations are those of conservation of species and overall mass. The finite element method is employed to handle this transient, two-dimensional, free boundary problem. It is found that local planarization is driven by large lateral concentration gradients that develop during drying, and by the presence before drying of a greater total mass of nonvolatiles per unit area where the film is thicker. The model is applied to isolated grooves and ridges and to a periodic array of grooves/ridges.

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“…For forming planar insulation layers, such techniques as applying polyimide insulation, etchback planarization, and SiO2 bias sputtering, have been developed (1)(2)(3). Bias sputtering of SiO2 has been a well-known technique that can simultaneously satisfy the first two of the above requirements (3).…”

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confidence: 99%

High‐Rate Planar SiO2 Deposition Using Magnetron Bias Sputtering

Homma

Tunekawa

1988

J. Electrochem. Soc.

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A high-rate bias sputtering technique, employing a planar magnetron cathode and RF power supplies with a phase shifter, was developed to form planar SiO2 films with a high deposition rate and low device damage. Utilizing the system, both the SiO2 deposition rate and the etch rate for resputtering were increased to several times higher than those in conventional method. The effects of substrate biasing and deposition temperature on SiO2 film quality were examined. Deposition temperature showed a stronger effect than substrate biasing on film quality, e.g., on the film's Ar content, refractive index, and etch rate by a buffered etch solution. The technique was applied to provide the planar interlevel insulation between two level interconnections for MOS VLSI test devices and showed significant improvement in step coverage and patterning accuracy in the second level metallization. It was also observed that there is little damage caused by the planar SiO2 deposition using this bias sputtering and it can be easily annealed out, making this technique applicable to MOS VLSI's.

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LSI Surface Leveling by RF Sputter Etching

Cited by 23 publications

References 4 publications

A surface modification process for silica microreactor array chips to seal aqueous solutions

A surface modification process for silica microreactor array chips to seal aqueous solutions

Mechanism for the Local Planarization of Microscopically Rough Surfaces by Drying Thin Films of Spin‐Coated Polymer/Solvent Solutions

High‐Rate Planar SiO2 Deposition Using Magnetron Bias Sputtering

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