High‐Rate Planar SiO2 Deposition Using Magnetron Bias Sputtering

Abstract

A high-rate bias sputtering technique, employing a planar magnetron cathode and RF power supplies with a phase shifter, was developed to form planar SiO2 films with a high deposition rate and low device damage. Utilizing the system, both the SiO2 deposition rate and the etch rate for resputtering were increased to several times higher than those in conventional method. The effects of substrate biasing and deposition temperature on SiO2 film quality were examined. Deposition temperature showed a stronger effect than substrate biasing on film quality, e.g., on the film's Ar content, refractive index, and etch rate by a buffered etch solution. The technique was applied to provide the planar interlevel insulation between two level interconnections for MOS VLSI test devices and showed significant improvement in step coverage and patterning accuracy in the second level metallization. It was also observed that there is little damage caused by the planar SiO2 deposition using this bias sputtering and it can be easily annealed out, making this technique applicable to MOS VLSI's.

Low Dielectric Constant Materials

“…Radio frequency (RF) bias sputtering of silica, which when done properly produces almost stoichimetric SiO 2 films with little SiOH, is quite slow and prone to particulate contamination. − Other sputtering techniques such as reactive sputtering, dual-ion sputtering, deposition by etching-enhanced reactive sputtering, etc. have been described but are not in common use in the BEOL for similar reasons as described above.…”

Wet chemical etching of silicate glasses in hydrofluoric acid based solutions

“…Etch rate results for as-deposited and heat-treated films have been reported for APCVD [58], LPCVD [84], PECVD [58, 79, 85-87-1, sputtering [76,88], sol-gel [75] and anodic SiO2 [77]. Reviews of the early work in IC technology were published in 1977 [74] and 1986 [72].…”

Double-level metal process for 1-μm technologies

“…New processes of materials need to be developped to obtain interlayer insulators ( i ) with good step coverage and void free filling of steep grooves, (ii) with total or partial planarization or capability to be planarised, (iii) with a short manufacturing time and no damaging of the underlying devices. Several techniques for forming planar insulation layers with high aspect ratios have been developped : polyimide (21), sandwich structure with permanent Spin On Glass (SOG) (22), SiO2 bias sputtering (23) and multiple deposition-etch process in a single tool (24).…”