Low-supply-noise Low-power Embedded Modular SRAM For Mixed Analog-digital ICs

Abstract

A low-power, low-noise embedded modular SRAM has been designed that dissipates 0.22 mWA4Hz and generates 25 mAlns dVdt for a 512 x 15 configuration at 3.3 V. Results are achieved using a pulsed divided word line architecture, with internal cascaded clocks, weak static sensing, low-noise buffers and flip-flops and low-power decoding techniques. 7.1.1 IEEE 1992 CUSTOM INTEGRATED CIRCUITS CONFERENCE 0-7803-0246-x/32 $3.00 1992 IEEE