BiCMOS technology for telecommunications

Many appllications would benefit from the availability of large-capakcity content addressable memories (CAM's). However, while RAM'S, EEPROM's, and other memory types achieve ever-increasing per-chip bit counts, CAM's show little promise of following suit, due primarily to an inherent difficulty in implementing two-dimensional decoding. The serialized operation of most proposed solutions is not acceptable in speed-sensitive environments. In response to the resulting need, this paper describes a fully-parallel (singleclock-cycle) CAM architecture that uses the concept of "preclassification" to realize a second dimension of decoding without compromising throughput. As is typically the case, each CAM entry is used as an index to additional data in a RAM. To achieve improved system integration, the preclassified CAM is merged into the same physical array as its target RAM, and both use the same core cells. Architecture and operation of the resulting novel memory are described, as are two critical-path circuits: the match-line pull-down and the multiple match resolver. The memory circuits, designed in 0.8 pm BiCMOS technology, may be employed in chips as large as 1 Mb, and simulations confirm 37 MHz operation for this capacity. To experimentally verify 1 he feasibility of the architectural and circuit design, an 8 kb lest chip was fabricated and found to be fully functional at clock speeds up to 59 MHz, with a power dissipation of 260 mW at 50 MHz.

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“…Conclusions follow in Section VII. A 0.8 pm BiCMOS ASIC process [6] is employed for all simulations, as well as for test chip implementation.…”

Section: Introduction N Content Addressable Memories (Cam's) Datamentioning

confidence: 99%